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engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-05_03,2026-11-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 malwarescore=0 adultscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611050045 On Thu, Nov 05, 2026 at 04:44:01AM +0000, Takahiro.Kuwano@infineon.com wrote: > Hi, > > > Add support for the ISSI IS25WX01G, a 1 Gbit (128 MiB) octal NOR flash. > > The part is fully described by SFDP, so only the flash ID and a small > > post_bfpt fixup are needed. > > > > WRITE STATUS REGISTER (01h) takes a single data byte and only affects > > status register bits 7:2, so the default 16-bit Write Status assumption > > does not hold. Clear write_sr1_and_sr2 so that the single byte write_sr1 > > path is taken; write_sr1 is already set to 01h by the BFPT parsing. > > > > The flash also has no Status Register 2. Configuration registers are read > > with B5h/85h and written with B1h/81h, and the 35h Read Configuration > > Register command does not exist, so clear read_sr2 as well. > > > > Software write protection is done through the block protect bits in the > > status register: BP0-BP2 at bits 4:2, BP3 at bit 6 and a Top/Bottom bit at > > bit 5, which is exactly what SPI_NOR_HAS_LOCK, SPI_NOR_4BIT_BP, > > SPI_NOR_BP3_SR_BIT6 and SPI_NOR_HAS_TB describe, so set those flags to get > > the generic locking support. > > > > Note that given that the Flag Status Register (FSR) handling is the same > > as in some micron devices, were're adding the issi chip directly on the > > micron-st driver. > > > > Signed-off-by: Nuno Sá > > Please add Link: tag as Michael mentioned in [1]. > > [...] > > > @@ -655,6 +680,7 @@ static const struct spi_nor_fixups micron_st_nor_fixups = { > > > > static const struct spi_nor_fixup micron_fixups[] = { > > { .fixups = µn_st_nor_fixups }, > > + { .id = SNOR_ID(0x9d, 0x5b, 0x1b), .fixups = &is25wx01g_fixups }, > > Sashiko's comment [2] looks valid to me as this chip supports 8D-8D-8D. > Could you please take a look? Thanks for taking a look! Will double check, thanks! - Nuno Sá > > Thanks, > Takahiro > > [1] https://lore.kernel.org/linux-mtd/DLETRRVRUWEP.1VU1EHARD3MSH@kernel.org/ > [2] https://sashiko.dev/#/patchset/20261102-mtd-spi-nor-new-issi-chip-v3-1-f5e38e200fc8%40analog.com >