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Thu, 05 Nov 2026 07:41:14 -0800 (PST) Received: from gmail.com ([2a03:2880:24ff:54::]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-67bee27bfddsm3766424d50.15.2026.11.05.07.41.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 07:41:14 -0800 (PST) Date: Thu, 5 Nov 2026 07:41:12 -0800 From: Breno Leitao To: Kiryl Shutsemau Cc: Catalin Marinas , Will Deacon , Mark Rutland , James Morse , Usama Arif , "Kiryl Shutsemau (Meta)" , Marc Zyngier , Doug Anderson , Jinjie Ruan , Ada Couprie Diaz , Vladimir Murzin , Linus Walleij , Peter Zijlstra , Thomas Huth , Dawei Li , mrigendrachaubey , kernel-team@meta.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH v2 2/2] arm64: sdei: Preserve the interrupted context's exception registers Message-ID: References: <20261105120835.3321912-1-kirill@shutemov.name> <20261105120835.3321912-3-kirill@shutemov.name> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261105120835.3321912-3-kirill@shutemov.name> On Thu, Nov 05, 2026 at 12:08:34PM +0000, Kiryl Shutsemau wrote: > From: "Kiryl Shutsemau (Meta)" > > An SDEI event is dispatched by firmware regardless of PSTATE.DAIF, so it > can interrupt the kernel where the exception registers are live: > > - exception entry, before kernel_entry has saved ELR_EL1/SPSR_EL1 and > before the C handler has read ESR_EL1/FAR_EL1; > - exception return, after kernel_exit has loaded ELR_EL1/SPSR_EL1 and > before the ERET. > > An IRQ or pseudo-NMI cannot arrive there with PSTATE.I set. Firmware > saves only x0-x17, PC and PSTATE around an SDEI event, so a synchronous > exception taken by the handler overwrites the interrupted context's > ELR, SPSR, ESR and FAR. do_sdei_event() only notices that ELR changed, > and warns. > > The interrupted context then carries on with the handler's state. A > task interrupted on its way into the kernel can be sent SIGILL for the > handler's kernel data abort. A task interrupted on its way back to user > space ERETs to EL1, at the handler's fixup address, with user registers > loaded. > > With SDEI delivering NMI backtraces, this happens in normal operation. > The handler runs show_regs(), which reads through possibly-NULL pointers > with the _nofault() accessors. print_worker_info() faults this way for a > kworker that is not running a work item, and a single sysrq-l warned > once per such kworker. > > Save ELR, SPSR, ESR and FAR in __sdei_handler() before > irqentry_nmi_enter(), which can take an exception too, and restore them > after irqentry_nmi_exit(). > > Once they are restored, a nested exception is harmless if its handler is > safe in NMI context. That holds for EL1 data aborts on translation, > permission and access-flag faults, which never take the mmap lock in NMI > context, and for BRK. Warn once, with the syndrome, about any other > exception class. > > Fixes: f5df26961853 ("arm64: kernel: Add arch-specific SDEI entry code and CPU masking") > Cc: stable@vger.kernel.org > Signed-off-by: Kiryl Shutsemau (Meta) Tested-by: Breno Leitao Tested on NVIDIA Grace (firmware SDEI) with next-20261104, KASAN + lockdep, ARM_SDEI_NMI=y: sysrq-l under stress-ng, with a kprobe on show_regs() and eprobes on irq_disable/irq_enable that fault on purpose. Without the series the box crashed (a task interrupted in el0t_64_sync got the handler's BRK, then lockdep/KASAN fallout and a hard lockup) With it, KPTI off and kpti=1, ~4000 kprobe hits and ~5500 faults in irqentry_nmi_enter()/exit() produced no warnings or stalls.