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a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=z/mQ4Ysz8XfWz/Q5cLBRGdckG28=:19 a=lCpzRmAYbLLaTzLvsPZ7Mbvzbb8=:19 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=M51BFTxLslgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=OmVn7CZJonkx5R5zMQLL:22 a=VwQbUJbxAAAA:8 a=qOIGJM2YW85aICZ6mjIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-GUID: 6VMhu1m1HsA63fZGNps-RPUI-9mUP_c8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-09_04,2026-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 clxscore=1015 malwarescore=0 adultscore=0 suspectscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611090047 On Sat, Nov 07, 2026 at 03:31:27PM +0800, Jisheng Zhang wrote: > On Thu, Oct 29, 2026 at 03:53:07PM +0000, Nuno Sá wrote: > > The Cadence xSPI driver currently drives every operation through STIG > > mode, where the CPU builds each command and drains the data. The > > controller also has an auto command (ACMD) mode where it runs whole > > sequences on its own and can move data with its internal DMA, which > > pays off for bulk reads. > > > > Whether ACMD and the internal DMA can be used depends on the SoC > > integration (external SRAM, the DMA bus requester interface being > > wired), which the controller registers do not expose. Hence two new > > devicetree properties: cdns,has-acmd and cdns,has-internal-dma. > > > > For now, ACMD is only used for reads of at least 2048 bytes with an > > address phase, using the internal DMA, and only when both properties > > are set. Smaller reads and all other operations stay on STIG. > > > > NOR and NAND are handled the same way: NAND operations are still issued > > one by one, not combined into a single ACMD sequence, so no NAND > > geometry is needed. The real gain is on large reads which, for NAND, > > means chips supporting buffer/sequential read mode. > > > > Another attempt for ACMD was sent in [1] but that relies on knowing the > > NAND geometry which brings much more complexity given that it needs a > > proper interface implemented in the spi-nand core. So we agreed on > > starting with this simpler approach and then build on top of it if we > > agree it pays off (mostly on cpu load). > > Hi Nuno, > > Thanks for this series though I can't test it because my platforms > disables the ACMD during integration. > > I just sent out a series to reduce the cpu load and improve performance > (possibly with powerful system memcpy dma engine), if your platforms > have the suitable memcpy dma engine, can you please try it? Sure, I'll give it a run and compare stats! I need to first tidy up my v2 and will test afterwards. Should happen this week! - Nuno Sá > > Hi Fei, > > can you plz try it too if your platform has suitable memcpy dma engine too? > > Thanks > > > > Some stats: > > > > ACMD > > ----- > > > > SPI-NOR - is25wx01g (only reads > 2k are done in ACMD ) > > ------- > > > > flash_speed -c 5 -d /dev/mtd4 > > not NAND flash, assume page size is 512 bytes. > > scanning for bad eraseblocks > > scanned 5 eraseblocks, 0 are bad > > testing eraseblock write speed > > eraseblock write speed is 1054 KiB/s > > testing eraseblock read speed > > eraseblock read speed is 106666 KiB/s > > testing page write speed > > page write speed is 1035 KiB/s > > testing page read speed > > page read speed is 15238 KiB/s > > > > SPI-NAND - w25n08lw (all reads are ACMD given that page size is 4k) > > -------- > > > > flash_speed -c 5 -d /dev/mtd5 > > scanning for bad eraseblocks > > scanned 5 eraseblocks, 0 are bad > > testing eraseblock write speed > > eraseblock write speed is 6497 KiB/s > > testing eraseblock read speed > > eraseblock read speed is 44137 KiB/s > > testing page write speed > > page write speed is 6336 KiB/s > > testing page read speed > > page read speed is 16842 KiB/s > > > > STIG > > ---- > > > > SPI-NOR > > ------- > > > > flash_speed -c 5 -d /dev/mtd4 > > not NAND flash, assume page size is 512 bytes. > > scanning for bad eraseblocks > > scanned 5 eraseblocks, 0 are bad > > testing eraseblock write speed > > eraseblock write speed is 1054 KiB/s > > testing eraseblock read speed > > eraseblock read speed is 64000 KiB/s > > testing page write speed > > page write speed is 1042 KiB/s > > testing page read speed > > page read speed is 14883 KiB/s > > > > SPI-NAND (Cont mode) > > -------- > > > > flash_speed -c 5 -d /dev/mtd5 > > scanning for bad eraseblocks > > scanned 5 eraseblocks, 0 are bad > > testing eraseblock write speed > > eraseblock write speed is 6564 KiB/s > > testing eraseblock read speed > > eraseblock read speed is 18823 KiB/s > > testing page write speed > > page write speed is 6400 KiB/s > > testing page read speed > > page read speed is 18028 KiB/s > > > > For now, we have a static threshold to decide to use ACMD or not. I do > > understand that's not ideal. It might depend on sclk and number of lanes > > so not sure if that value will be accurate for everybody. So, open to > > suggestions if someone has something in mind regarding this. > > > > [1]: https://lore.kernel.org/linux-spi/20260921093701.1341766-1-fei.xie@horizon.auto/ > > > > --- > > Nuno Sá (3): > > spi: cadence-xspi: rename sdma_error to xfer_error > > spi: dt-bindings: cdns,xspi: add ACMD and internal DMA properties > > spi: cadence-xspi: add ACMD mode support > > > > .../devicetree/bindings/spi/cdns,xspi.yaml | 18 ++ > > drivers/spi/spi-cadence-xspi.c | 269 +++++++++++++++++++-- > > 2 files changed, 273 insertions(+), 14 deletions(-) > > --- > > base-commit: 7da2aca123754c0e06092bbe179d58078b58d8d4 > > change-id: 20261027-xspi-cadence-add-acmd-3c0e342cb4f4 > > -- > > > > Thanks! > > - Nuno Sá > >