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[35.189.192.250]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4b90619bbd2sm134824845e9.1.2026.11.09.03.37.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 03:37:04 -0800 (PST) Date: Mon, 9 Nov 2026 11:37:00 +0000 From: Mostafa Saleh To: Nicolin Chen Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, iommu@lists.linux.dev, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, joro@8bytes.org, jgg@ziepe.ca, mark.rutland@arm.com, qperret@google.com, tabba@google.com, vdonnefort@google.com Subject: Re: [PATCH v9 14/25] iommu/arm-smmu-v3-kvm: Shadow the command queue Message-ID: References: <20261015200903.2735565-1-smostafa@google.com> <20261015200903.2735565-15-smostafa@google.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Thu, Nov 05, 2026 at 05:59:33PM -0800, Nicolin Chen wrote: > One more thing: > > On Thu, Oct 15, 2026 at 08:08:45PM +0000, Mostafa Saleh wrote: > > +/* > > + * The kernel part of the driver allocates and zeroes the shadow cmdq. Take > > + * ownership of it and program it into the hardware. > > + */ > > +static int smmu_init_cmdq(struct hyp_arm_smmu_v3_device *smmu) > > +{ > > + size_t cmdq_nr_pages; > > + int ret; > > + > > + smmu->cmdq.llq.max_n_shift = min(smmu->cmdq.llq.max_n_shift, smmu->cmdq_max_shift); > > Given this is the cmdq used to run commands eventually.. > > > +static void smmu_emulate_cmdq_enable(struct hyp_arm_smmu_v3_device *smmu) > > +{ > > + u32 shift = smmu->cmdq_host.q_base & Q_BASE_LOG2SIZE; > > + > > + smmu->cmdq_host.llq.max_n_shift = min(shift, smmu->cmdq_max_shift); > > .. should this be min(shift, smmu->cmdq.llq.max_n_shift)? > > Otherwise, a buggy guest SW might setup a larger queue and number > of commands? Makes sense, as in patch#16, it caps the host view in the emulated IDR1: val = readl_relaxed(smmu->base + ARM_SMMU_IDR1); val &= ~IDR1_CMDQS; val |= FIELD_PREP(IDR1_CMDQS, smmu->cmdq.llq.max_n_shift); Thanks, Mostafa > > Nicolin