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micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="paljnoslhkxoag7v" Content-Disposition: inline In-Reply-To: <20261109173329.GA252206@bhelgaas> X-Zoho-Virus-Status: 1 X-Zoho-AV-Stamp: zmail-av-0.7.7.1.5.4/291.452.71 X-ZohoMailClient: External --paljnoslhkxoag7v Content-Type: text/plain; protected-headers=v1; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH v9 1/9] PCI: dw-rockchip: Fix LTSSM set functions MIME-Version: 1.0 Hi, On Mon, Nov 09, 2026 at 11:33:29AM -0600, Bjorn Helgaas wrote: > On Thu, Nov 05, 2026 at 02:33:09PM +0100, Sebastian Reichel wrote: > > Before the Rockchip PCIe driver has been switched over to the > > FIELD_PREP_WM16 macro, PCIE_CLIENT_ENABLE_LTSSM and > > PCIE_CLIENT_DISABLE_LTSSM were setting bits with a mask of 0xc =3D 0b11= 00, > > which means BIT 2 and BIT 3. After the conversion it only sets bit 2, > > with bit 3 being handled by a separate define named > > PCIE_CLIENT_LD_RQ_RST_GRT. Apparently the conversion missed to make use > > of this new macros resulting in the third bit not being set. > >=20 > > Fixes: 30e919570581 ("PCI: dw-rockchip: Switch to FIELD_PREP_WM16 macro= ") >=20 > This commit appeared in v6.18, so this looks like it might be a > candidate for a stable tag? IDK if its worth backporting. I mainly did not add the tag, since I found this by chance while rebasing code around it. For my basic tests I didn't notice any problems even without the bit. Also nobody reported anything since v6.18. The bit was originally set since the driver had been introduced. Maybe Shawn can say if its worth backporting? Greetings, -- Sebastian >=20 > > Reviewed-by: Shawn Lin > > Signed-off-by: Sebastian Reichel > > --- > > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 10 ++++++---- > > 1 file changed, 6 insertions(+), 4 deletions(-) > >=20 > > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pc= i/controller/dwc/pcie-dw-rockchip.c > > index bd86e32cc2b1..c35c5583c797 100644 > > --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c > > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > > @@ -322,14 +322,16 @@ static void rockchip_pcie_ltssm_trace(struct rock= chip_pcie *rockchip, > > =20 > > static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) > > { > > - rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, > > - PCIE_CLIENT_GENERAL_CON); > > + u32 val =3D PCIE_CLIENT_ENABLE_LTSSM | PCIE_CLIENT_LD_RQ_RST_GRT; > > + > > + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_GENERAL_CON); > > } > > =20 > > static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip) > > { > > - rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM, > > - PCIE_CLIENT_GENERAL_CON); > > + u32 val =3D PCIE_CLIENT_DISABLE_LTSSM | PCIE_CLIENT_LD_RQ_RST_GRT; > > + > > + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_GENERAL_CON); > > } > > =20 > > static bool rockchip_pcie_link_up(struct dw_pcie *pci) > >=20 > > --=20 > > 2.53.0 > >=20 --paljnoslhkxoag7v Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE72YNB0Y/i3JqeVQT2O7X88g7+poFAmryCuYACgkQ2O7X88g7 +pogbxAAp7uNHMud1soRc7aXKsYq8Hhj71CnA/0igLKhPz2fe9QBAQVtTB89jIcU brCPZy3/1yY4VdnZkFZWxaCip+XoK2JzI5QKdzoT9YK5KQ5o28Qi0JeJEgi5BdPm CMTLEg6ctaPRBpKllRV3Bn+2WiYatx+CnDSsRyWvnE+4oXg2mqsIHpJaUTVfN+Tp JdAr1mSvTZVUw6MfOqk6Of8MFngTOB294cqYq7a65l27Snz+xG6kIGkGcYn04ffa saelnMsjj70mS+h3qYtLVo2MOiUMYqEabJXlN++qnt3eTIdfT0zRItDztDKEdE/x qsQ/Vo4hpfvBH2YjwCPPwt30iZwmCs8zOifkQz+Hb7FzyzRg39G7sMw69aO7qVit Y8U4b6GiAXGZC9+bQ7hcURgdpH3Aq+qJtsb2tPs2MGmPCWYlMMMcHdxYHLG9l1yd VVg1eSWEruxled/h6TU79ZuUWC5qO0asV6aookwlekGo2hgMrdLpIvTUr+3XygGI SGaPsuLhSAveEXkoqGGFO0gXWN3aY3aDnSxvksZEjiTygaw9pmF1bBvfeo4tso9V VCAVzrmkDsab86TF1qy89KOuaWAzXXNJ6lGMuGHCeEXPssT/cdA8vEIpbErYPaFi oZIXu8VaDL1jTPN3YxbyTPnLw15ijtb2W/Dhv2NGJx/y2PBXnGQ= =ATM0 -----END PGP SIGNATURE----- --paljnoslhkxoag7v--