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a="2995970" X-IronPort-AV: E=Sophos;i="6.27,204,1787036400"; d="scan'208";a="2995970" Received: from fmviesa011.fm.intel.com ([10.60.135.151]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Nov 2026 14:49:55 -0800 X-CSE-ConnectionGUID: g8JDfDVAS4SVWzVWmZmJxg== X-CSE-MsgGUID: vtYgExP0SwSsDgFv8Tk78g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,204,1787036400"; d="scan'208";a="9770089" Received: from amilburn-desk.amilburn-desk (HELO localhost) ([10.245.244.144]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Nov 2026 14:49:53 -0800 Date: Tue, 10 Nov 2026 00:49:51 +0200 From: Andy Shevchenko To: James Hilliard Cc: Eugeniy Paltsev , Vinod Koul , Frank Li , Sergey Khimich , Sia Jee Heng , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH 1/3] dmaengine: dw-axi-dmac: poll the correct enable bit during termination Message-ID: References: <20261108-submit-dw-axi-dma-stop-pause-v1-v1-0-c48ec19e9ee4@gmail.com> <20261108-submit-dw-axi-dma-stop-pause-v1-v1-1-c48ec19e9ee4@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261108-submit-dw-axi-dma-stop-pause-v1-v1-1-c48ec19e9ee4@gmail.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Sun, Nov 08, 2026 at 10:02:36PM -0700, James Hilliard wrote: > For channels 16 through 31, the channel enable bits occupy bits 32 through > 47 of the extended DMAC_CHEN register. dma_chan_terminate_all() only reads > the low word and tests BIT(chan->id), so it can conclude that an upper-bank > channel has stopped while its actual enable bit remains set. Descriptors > can then be freed while hardware still owns them. > > Poll axi_chan_is_hw_enable(), which already handles both register banks > and the smaller channel layouts, instead of constructing another mask. ... > - ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val, > - !(val & chan_active), 1000, 50000); > + ret = read_poll_timeout_atomic(axi_chan_is_hw_enable, enabled, !enabled, > + 1000, 50000, false, chan); With a single argument it's readx_poll_timeout_atomic(). While at it, you may use 1 * USEC_PER_MSEC and 50 * USEC_PER_MSEC instead of plain numbers. ret = readx_poll_timeout_atomic(axi_chan_is_hw_enable, chan, enabled, !enabled, 1 * USEC_PER_MSEC, 50 * USEC_PER_MSEC); -- With Best Regards, Andy Shevchenko