Hi,

On Tue, Nov 10, 2026 at 07:11:48AM +0000, Arun Iyengar via B4 Relay wrote:
> From: Arun Iyengar <aiyengar1990@gmail.com>
> 
> An SMMUv3 instance can sit in a switchable power domain of the SoC, for
> example the MMU-600 in front of the PCIe controllers on the Rockchip
> RK3588, which is part of the PCIe power domain. If the domain is not
> described, nothing keeps it powered while the SMMU is bound, and any
> register access after it has been turned off as unused stalls the
> interconnect.
> 
> Allow a single power-domains entry, as arm,smmu.yaml already does for
> the earlier SMMU architectures.
> 
> Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
> ---

Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>

Greetings,

-- Sebastian

>  Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> index 3c044e4f03d4..c8f22dfdb1db 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> @@ -63,6 +63,9 @@ properties:
>  
>    msi-parent: true
>  
> +  power-domains:
> +    maxItems: 1
> +
>    nvidia,cmdqv:
>      description: |
>        A phandle to its pairing CMDQV extension for an implementation on NVIDIA
> 
> -- 
> 2.55.0
> 
> 
>