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c=relaxed/relaxed; s=zohomail; d=collabora.com; v=1; bh=1nscl7aZNwOtv842vwFmJ0HuXa6txcAWMb0wIM3bg7A=; h=Content-Description:Content-ID:Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Owner:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Resent-Sender:Resent-Cc:Resent-Date:Resent-To:Reply-To:Resent-Message-ID:Resent-From:Sender:Subject:To:Date:From:Message-Id:Reply-To:Subject:To:Cc; Received: by smtp.zohomail.com with SMTPS id 1794322422153362.1328994697353; Tue, 10 Nov 2026 06:53:42 -0800 (PST) Received: by venus (Postfix, from userid 1000) id A4C1E180354; Tue, 10 Nov 2026 15:53:28 +0100 (CET) Date: Tue, 10 Nov 2026 15:53:28 +0100 From: Sebastian Reichel To: aiyengar1990@gmail.com Cc: Will Deacon , Robin Murphy , "Joerg Roedel (AMD)" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org Subject: Re: [PATCH 3/5] iommu/arm-smmu-v3: enable optional clocks Message-ID: References: <20261110-smmu-v3-pcie-pd-v1-0-628819ca44b9@gmail.com> <20261110-smmu-v3-pcie-pd-v1-3-628819ca44b9@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="j6dulos5oufpuo7z" Content-Disposition: inline In-Reply-To: <20261110-smmu-v3-pcie-pd-v1-3-628819ca44b9@gmail.com> X-Zoho-Virus-Status: 1 X-Zoho-AV-Stamp: zmail-av-0.2.13.1.5.4/294.310.16 X-ZohoMailClient: External --j6dulos5oufpuo7z Content-Type: text/plain; protected-headers=v1; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH 3/5] iommu/arm-smmu-v3: enable optional clocks MIME-Version: 1.0 Hi, On Tue, Nov 10, 2026 at 07:11:50AM +0000, Arun Iyengar via B4 Relay wrote: > From: Arun Iyengar >=20 > On some platforms the SMMU's clock is controlled by the OS, and without a > consumer the clock framework gates it as unused late in boot. Any later > register access, for example the CR0 write in the shutdown path, then > stalls the interconnect. This happens on the RK3588 when no PCIe > controller keeps the PCIe MMU-600 clock running. >=20 > Get and enable all clocks described in the firmware node before the > registers are first accessed, and keep them enabled while the driver is > bound. Nodes without clocks are not affected. >=20 > Signed-off-by: Arun Iyengar > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 7 +++++++ > 1 file changed, 7 insertions(+) >=20 > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/= arm/arm-smmu-v3/arm-smmu-v3.c > index 6d4520c47308..cce66db93219 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -12,6 +12,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -5786,6 +5787,7 @@ static int arm_smmu_device_probe(struct platform_de= vice *pdev) > resource_size_t ioaddr; > struct arm_smmu_device *smmu; > struct device *dev =3D &pdev->dev; > + struct clk_bulk_data *clks; > =20 > smmu =3D devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); > if (!smmu) > @@ -5800,6 +5802,11 @@ static int arm_smmu_device_probe(struct platform_d= evice *pdev) > if (ret) > return ret; > =20 > + /* Optional clocks: keep them running for as long as we are bound */ useless comment, otherwise Reviewed-by: Sebastian Reichel Greetings, -- Sebastian > + ret =3D devm_clk_bulk_get_all_enabled(dev, &clks); > + if (ret < 0) > + return dev_err_probe(dev, ret, "failed to enable clocks\n"); > + > smmu =3D arm_smmu_impl_probe(smmu); > if (IS_ERR(smmu)) > return PTR_ERR(smmu); >=20 > --=20 > 2.55.0 >=20 >=20 >=20 --j6dulos5oufpuo7z Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE72YNB0Y/i3JqeVQT2O7X88g7+poFAmrzL+gACgkQ2O7X88g7 +prUgg/+JNEo0SPEnyobWdRYPSOZu/Tn9RCGlBzIehkk0TD0d2SvMuDPacuxM6iy msiz8nlhpfkagYAKp9ojnjS8MIDJ98u/AihAlgXj6PaLeWVLhUaN62zkKgYEB7pN eAK6AZNCaLAKTDfQUhnAS5Ts4DFqhfo2kURK/5sLoKgvgCEIVJIBQsISRtOgxnYp w+rqmAj1so634w7NXLzLt2hCL93EZxSfQWJFjWzAX4pSR0YtRYM+g9NZiO2G/YHj Aip92FBnkjVXbl0+DAPnQJ3PTjWIWABxwp4DLs/WfkiOHSv59z6rXW7iluR/+5y1 6e2T21bQnoAmbGsTKpZbTT6UUkLCfXDfIc4bIFqWQR604Gb37xENkUsq8elOzIfT oj4ObXRhUCUlurV2tVjAmYqlbXKrVEEhI+pnTvbg3aNmj/12fT5wtOZsaSGg8FVW nTjMYzcj+geSNOKvi/asIOFV8jR6fIl7TwOS7u/ojoTlCvAJ2V77g8l5+u/8qnA/ Phw3tKaaoahqi7m84zxDyc1oXAwvUvz0kDZIg8ZEUm6fRr1W53LILDMvMgIrRTcL qmzlHQJlx+PhspiX+kE7kwCp8dFmhcndqnlZwsTcIdxkGJJQnhM0Anrq0k3x6omB OI5FfL+iINUvWHew81mwzujVKxBgxcYpbbfxo2ySecCSc5HmH0A= =10on -----END PGP SIGNATURE----- --j6dulos5oufpuo7z--