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Brown" > > The hs_zero timing is computed as > > n = (144 * (hs_clk_rate / 1000000) - 47500) / 10000; > cfg->m_prg_hs_zero = n < 1 ? 1 : n; > > hs_clk_rate is an unsigned long, so the subtraction is done unsigned and > wraps for any rate below about 330 MHz, where 144 * MHz < 47500. Because > n is a u32, the wrapped value is never seen as negative and the "n < 1" > clamp does not take effect. The garbage value is then truncated into the > 8-bit m_prg_hs_zero register field. At the minimum supported rate of > 80 MHz this programs 199 on 64-bit and 181 on 32-bit, instead of the > intended minimum of 1. > > Make n signed and do the arithmetic in int so the clamp works on both > 32-bit and 64-bit. The divided rate is at most 1500, so 144 * 1500 fits > easily in an int. > > Fixes: f4c8116e294b ("phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCs") > Cc: stable@vger.kernel.org > Signed-off-by: Oliver F. Brown > Signed-off-by: Stefan Ghetu Reviewed-by: Laurentiu Palcu -- Thanks, Laurentiu