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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: V9xa4ytZMB7MaVuIbrpPJNHNDDilADb08ROUavpEVlCMEhSqto16sJRjO69o6vlong3IrUtT4rd2u7OsEdYYnxm5xw4J9Ok4ecmorGDTZISNqbhK/XhTLfCwLCBDRntB01cSHpgPn9q8HBzr/wa9i4Oc4JiseFw4wO6fB7EUyHVMYip37B2T/9xwDAuC+LxxEPcWlAJ0dVLAlzNkwgbaLF2ZNM67DE9JXpyMzbx2F4cxgpGFznGIm5XfTBUBX/Fna+u41M+6CLomSyUrY4J/ouqYYcjVh2OJgNT4zHsEKa8uVx34ikM1vtYFezFpTU20TCTCGfu3kMFUhML4hlm8pY8+tMEAClTQpFdgWBfwXApWLyhek0E7h89hLqaja3NZpRW0SlCIOhIpNbMQJSKFe0sJfegf/4fobBN2ptbGFmVY0/eWHrrOj58ZkyrSuSrd X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2026 18:25:30.4057 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ca06cb32-3698-40b9-50e6-08df3f58005f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN5PEPF00046987.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV1PR12MB399762 On Tue, Nov 10, 2026 at 10:41:27AM +0000, Mostafa Saleh wrote: > On Mon, Nov 09, 2026 at 04:16:53PM -0800, Nicolin Chen wrote: > > On Mon, Nov 09, 2026 at 10:47:46AM +0000, Mostafa Saleh wrote: > > > On Thu, Nov 05, 2026 at 01:06:18PM -0800, Nicolin Chen wrote: > > > > On Thu, Oct 15, 2026 at 08:08:42PM +0000, Mostafa Saleh wrote: > > > > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > > > > +#ifdef CONFIG_ARM_SMMU_V3_PKVM > > > > > +/* > > > > > + * Two devices are involved: the aux device bound to this driver, and the > > > > > + * physical platform device bound to the pKVM init driver, which only uses it > > > > > + * for discovery. This driver keeps using the platform device, as it carries > > > > > + * the fwnode the IOMMU core and consumers link to, the DMA configuration and > > > > > + * the IRQs. > > > > > > > > It would be nicer to have a diagram or so to show the co-relationship > > > > among different devices and drivers. > > > > > > > > I assume the regular arm-smmu-v3 driver is a part of the picture too, > > > > when the pkvm driver binding fails? > > > > > > > > > > I can add some ASCII diagram. > > > If pKVM driver fails, no aux devices are created and the main driver > > > probes the platform SMMUv3 devices as usual. > > > > I didn't check closely, but would it be safe to do so? > > > > Is pkvm aware of the missing SMMU device and handling it properly? > > > > When pkvm is enabled and the SMMU device is supposed to be a pkvm > > device, should it not fall back to the main driver? > > If pKVM fails to init for any reason (unsupported layout or non-coherent > HW) the SMMU will be bound to the main driver so the system remains > functional. > > However, pKVM will not be safe in that case regarding DMA isolation > as the status quo. > In Android, in that case, pKVM clears the FW (called pvmfw) that loads > the protected VM and authenticate it so any protected VM knows the > system is not trusted. This part is not upstream yet. [1] You might want to double check a dual-SMMU case, where one gets accepted by pkvm driver and the other fails and so bound to the main driver. It seems the pkvm driver would still pkvm_iommu_register_driver and carry on with an untrusted SMMU. Would it also clear the FW and mark the system as not trusted? Nicolin