On Wed, Oct 28, 2026 at 12:51:20PM +0000, Biju Das wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> The clock divider on the RZ/G3L SoC is 11 bits wide, which needs a
> clock mask of 0x200000200 in renesas_sdhi_set_clock() instead of the
> hardcoded 0x80000080 used so far.
> 
> Add a u64 clk_mask field to struct renesas_sdhi_of_data and struct
> tmio_mmc_data so SoC-specific match data can supply its own mask, and
> widen the clk and clock variables in renesas_sdhi_set_clock() from
> u32 to u64 to hold it.
> 
> While at it, clamp the initial clock value to a minimum of 1. If
> actual_clock / 512 evaluates to 0, the loop condition
> "new_clock + clk_margin >= (clock << 1)" is always true, and the
> loop never terminates.
> 
> In probe, copy clk_mask from the OF data and fall back to
> SDHI_CLK_MASK_DEFAULT when none is provided, so existing
> SoCs keep their current behaviour.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>