On Wed, Oct 28, 2026 at 12:51:23PM +0000, Biju Das wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Add a clk_div_mask field to renesas_sdhi_of_data and tmio_mmc_data
> so each SoC can specify its own divider mask instead of the
> hardcoded CLK_CTL_DIV_MASK used in renesas_sdhi_set_clock().
> 
> Default to CLK_CTL_DIV_MASK at probe time when unset.
> This lets RZ/G3L, which has a wider divider field, reuse the same
> clock-setting code.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>