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a=rsa-sha256; c=relaxed/relaxed; d= sang-engineering.com; h=date:from:to:cc:subject:message-id :references:mime-version:content-type:in-reply-to; s=k1; bh=lp+t 3hRjxL5IFyviaZjgCI7gTo2Zcgy+Stw2L1SIlYc=; b=W3eeflARskWQiVTIXBlj 28P69SPEnCj5IW0/mTi68CZanbLA6BWZU9u8x6veYMkwvNglY213Ub6N5LWthoPM Ka/T+TUU5e/xq0gj/KYkSdo3fx1rwiuPm9S/TmzcBUDqonliVVTkelowKKsXUmpc uDmTKAJnv616MP2/YeTT7OutnKjw9iWiA4lPI8AXzlkUfiA7xvemItsnYnef/q9a vAZ2XGOA/g+WyknOkdv0B9tIMRZPOZyhlKkE0lxx/JIzJq+5nikrT7aG+JMbUCJi BXHGmkD421FGmDOp0QM141NXGGvKqYkDhIvAi8+f/lzv0vkkV3zWEVfw0TXyPSB8 Ig== Received: (qmail 565967 invoked from network); 11 Nov 2026 11:14:54 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 11 Nov 2026 11:14:54 +0100 X-UD-Smtp-Session: l3s3148p1@FdJdd/1fDrQujnun Date: Wed, 11 Nov 2026 11:14:54 +0100 From: Wolfram Sang To: Biju Das Cc: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Philipp Zabel , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: Re: [PATCH v25 06/11] mmc: renesas_sdhi: Make clock divider mask configurable Message-ID: References: <20261028-rzg3l_sdhi-v25-0-57f16691c2ed@bp.renesas.com> <20261028-rzg3l_sdhi-v25-6-57f16691c2ed@bp.renesas.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="YRG0+FJlDArByPdA" Content-Disposition: inline In-Reply-To: <20261028-rzg3l_sdhi-v25-6-57f16691c2ed@bp.renesas.com> --YRG0+FJlDArByPdA Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Oct 28, 2026 at 12:51:23PM +0000, Biju Das wrote: > From: Biju Das >=20 > Add a clk_div_mask field to renesas_sdhi_of_data and tmio_mmc_data > so each SoC can specify its own divider mask instead of the > hardcoded CLK_CTL_DIV_MASK used in renesas_sdhi_set_clock(). >=20 > Default to CLK_CTL_DIV_MASK at probe time when unset. > This lets RZ/G3L, which has a wider divider field, reuse the same > clock-setting code. >=20 > Signed-off-by: Biju Das Reviewed-by: Wolfram Sang --YRG0+FJlDArByPdA Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEOZGx6rniZ1Gk92RdFA3kzBSgKbYFAmr0QB4ACgkQFA3kzBSg Kbbg8g/8D7xNXyQjqyFx4RqHuX+IddyMKkIytq3+COoau4CUejcf+eSMuqflgFcb foDKzXOqbaiAkbQ3XPiU3BQ37kZTAtu69uhXXK8zKtqXcVhwDE9808s15Q+qrXz4 47I6Uemj/7fwj2+MstmTOW7ANwQZwZcSAf/tEMVUUWLQyRlSNkW1Dy+cx+BaQTYE +o+b0DUbeRnqdsQL4kRuHwbgCBv4iHKuFJE2UeL5MMdIgLYSKa3QzD6oHAQ1LZxE Wtxg4hc2IoNyZ7VDEMrokSsx4znNk+QjYpOBKrjtps6QP0rek0MRMRwKUb5Uezz8 Oe3OLiqCojmdx9vwhZSvShcW1g8JTyWZc8DXyz57i3sVxqtG+t22xX4YXT4AAiLV Xdy+6EpPEJchO1rNnxJ5c8ks5pb7atFX4dzOgXuMhODUGzmXWCcUL3TvUp8LTcqN Q+zE1/ck1qjfpqHydF4U7qKo9dZ0muiI2a7lnpK5h7sjHimO7rIwmZ0u0pxgfYmk tLxPDcveKbvJMS65uFHobqe11Qqz6ApxH7RhM4PWhNvehGuv8RlHEj8+mH0RvEC9 4pPcinB4Oqp1TZymO3DK9GJC9guCfYCk1+AFF2Ij5/8p120aLdI0gcNhgozVkvB7 2pXT5f+WBP2V82GRoDxaxIvbrksdN2rIsgWfBuawj5IL42rpJvY= =76PA -----END PGP SIGNATURE----- --YRG0+FJlDArByPdA--