On Wed, Oct 28, 2026 at 12:51:24PM +0000, Biju Das wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> RZ/G2L and later SoCs (RZ/V2M and RZ/G3E) need a hardware adjustment
> delay written to SCC_TMPPORT2 on signal-voltage switch during
> tuning: 0x1 for 1.8V, 0x0 for 3.3V.
> 
> Add a TMIO_MMC_TUNING_DELAY flag and
> renesas_sdhi_set_hw_adjustment_delay(), called from
> renesas_sdhi_start_signal_voltage_switch() after the regulator is
> set, and reset SCC_TMPPORT2 to 0 at the start of
> renesas_sdhi_execute_tuning() when the flag is set and tap_num == 8.
> 
> Add a dedicated of_data_rz_g2l descriptor with this flag and switch
> of_rzg2l_compatible to use it instead of the generic R-Car Gen3
> descriptor.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>