On Wed, Oct 28, 2026 at 12:51:25PM +0000, Biju Das wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> RZ/G3L has a fixed internal /2 clock divider active in all bus
> timing modes except HS400, where the divider is bypassed. Add a
> TMIO_MMC_INTERNAL_DIVIDER flag to mark controllers with this
> divider.
> 
> Add renesas_sdhi_clk_get_rate() to fold the /2 division into the
> reported clock rate when the flag is set, and use it in
> renesas_sdhi_clk_update() in place of clk_get_rate(). HS400 is not
> yet supported in software for this SoC. Adjust clkh_shift for the
> internal divider case.
> 
> No existing platform sets this flag, so this is infrastructure only,
> with no functional change for current SoCs.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

> +	/*
> +	 * The clock driver may not know the maximum working frequency, so it
> +	 * should come from the 'max-frequency' property. If it is missing,
> +	 * assume the current rate is the maximum. SoCs with an internal
> +	 * divider can't do that, because the current rate is not
> +	 * meaningful for them, so the property is mandatory there.
> +	 */

Good description!