On Wed, Oct 28, 2026 at 12:51:28PM +0000, Biju Das wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> The RZ/G3L SDHI is close to existing variants but differs in three
> ways the driver can't handle today:
> 
> - It has an 11-bit clock divider. The upper bits live in CLK_CTL
>   bits [17:16], so the register must be written with a 32-bit access
>   on this SoC.
> - Tuning needs a second HW adjustment register (HWADJ2), programmed
>   together with TMPPORT2.
> - HWADJ4 must be cleared when tuning starts.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

I like the renesas_sdhi_sclken() helper.

All review done, congrats! I will run some tests on R-Car hardware in
a few minutes.