> The GPIO register offsets are private to pinctrl-airoha.c, which builds
> the shared 64 pin register table from them. A SoC with more GPIO banks
> needs its own table, built from the same offsets and its own for the
> extra banks.
> 
> Move the offsets to airoha-common.h so the SoC drivers can use them.
> 
> No functional change.

Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>

> 
> Signed-off-by: John Crispin <john@phrozen.org>
> ---
>  drivers/pinctrl/airoha/airoha-common.h  | 20 ++++++++++++++++++++
>  drivers/pinctrl/airoha/pinctrl-airoha.c | 20 --------------------
>  2 files changed, 20 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
> index adfce89493f0..dc9b897ea77c 100644
> --- a/drivers/pinctrl/airoha/airoha-common.h
> +++ b/drivers/pinctrl/airoha/airoha-common.h
> @@ -34,6 +34,26 @@
>  #include "../pinconf.h"
>  #include "../pinmux.h"
>  
> +/* GPIOs */
> +#define REG_GPIO_CTRL				0x0000
> +#define REG_GPIO_DATA				0x0004
> +#define REG_GPIO_INT				0x0008
> +#define REG_GPIO_INT_EDGE			0x000c
> +#define REG_GPIO_INT_LEVEL			0x0010
> +#define REG_GPIO_OE				0x0014
> +#define REG_GPIO_CTRL1				0x0020
> +#define REG_GPIO_CTRL2				0x0060
> +#define REG_GPIO_CTRL3				0x0064
> +#define REG_GPIO_DATA1				0x0070
> +#define REG_GPIO_OE1				0x0078
> +#define REG_GPIO_INT1				0x007c
> +#define REG_GPIO_INT_EDGE1			0x0080
> +#define REG_GPIO_INT_EDGE2			0x0084
> +#define REG_GPIO_INT_EDGE3			0x0088
> +#define REG_GPIO_INT_LEVEL1			0x008c
> +#define REG_GPIO_INT_LEVEL2			0x0090
> +#define REG_GPIO_INT_LEVEL3			0x0094
> +
>  #define AIROHA_NUM_PINS				64
>  #define AIROHA_PIN_BANK_SIZE			(AIROHA_NUM_PINS / 2)
>  #define AIROHA_REG_GPIOCTRL_NUM_PIN		(AIROHA_NUM_PINS / 4)
> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index a805f542bc7b..8f901f251c00 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -7,26 +7,6 @@
>  
>  #include "airoha-common.h"
>  
> -/* GPIOs */
> -#define REG_GPIO_CTRL				0x0000
> -#define REG_GPIO_DATA				0x0004
> -#define REG_GPIO_INT				0x0008
> -#define REG_GPIO_INT_EDGE			0x000c
> -#define REG_GPIO_INT_LEVEL			0x0010
> -#define REG_GPIO_OE				0x0014
> -#define REG_GPIO_CTRL1				0x0020
> -#define REG_GPIO_CTRL2				0x0060
> -#define REG_GPIO_CTRL3				0x0064
> -#define REG_GPIO_DATA1				0x0070
> -#define REG_GPIO_OE1				0x0078
> -#define REG_GPIO_INT1				0x007c
> -#define REG_GPIO_INT_EDGE1			0x0080
> -#define REG_GPIO_INT_EDGE2			0x0084
> -#define REG_GPIO_INT_EDGE3			0x0088
> -#define REG_GPIO_INT_LEVEL1			0x008c
> -#define REG_GPIO_INT_LEVEL2			0x0090
> -#define REG_GPIO_INT_LEVEL3			0x0094
> -
>  #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val)			\
>  	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,		\
>  				(pin), (val))
> -- 
> 2.34.1
>