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Wed, 11 Nov 2026 11:22:35 -0800 (PST) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-37520512ec1sm17793328eec.12.2026.11.11.11.22.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2026 11:22:35 -0800 (PST) Date: Thu, 12 Nov 2026 00:52:27 +0530 From: Abhinaba Rakshit To: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Adrian Hunter , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neeraj Soni , Harshal Dev , Kuldeep Singh Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio Subject: Re: [PATCH v12 0/6] Enable ICE clock scaling Message-ID: References: <20260824-enable-ice-clock-scaling-v12-0-09271f583dc6@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260824-enable-ice-clock-scaling-v12-0-09271f583dc6@oss.qualcomm.com> X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTExMDA3NyBTYWx0ZWRfX6klJW2/sQQmA TuSYc9iG4UheVDBaVUcapAqv39mSKgfZwGoevGD7CdYj1nVoT09JZk1PgMTMt1Lz+/tZ0QGr+Tw in5hKp0rOtQWL3ksnx1FwPyC4jT/ISOESM3Ek78K89rmHQdohtN4AAp2APKI0WyXLFAQ202wAqA 8GWPomdc7pYwh4ia1HhCfbQ2DTnnRuCJzU759UmtFbSa221hrUU/NIi0OCcTeWgy6BbWK1/5RtZ j+4ajJ3jye4Pd+cTdmSV5Fcao5nuzCrTCmkbi/zdgE8L8UjVjy8OTTMJJfOrOF+YdX9j0exuvzS KNhX5H3VtrP0gCAPQ16hQmiw0xkPvoUSKaKkrg/Y+Fzl9ZHf6cr4gj04o2Wb+jTkMO35FZ29l87 XXy//msg0BXAkrFFUv4wK4JttJTdqoxbmanEM7vgSeCdy4BcYaF/HxefW686YS1PqtFC7nMaEA1 SImMQBMAxUvcL+TvFPw== X-Proofpoint-ORIG-GUID: sutgCUHG-Wsyz68fm_2ptnr3u6YOgXZy X-Authority-Analysis: v=2.4 cv=FeuiV5+6 c=1 sm=1 tr=0 ts=6af4c07d cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=FeIq2xlXlOKQ0BwA5tkA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-GUID: sutgCUHG-Wsyz68fm_2ptnr3u6YOgXZy X-Proofpoint-Spam-Info: AW1haW4tMjYxMTExMDA3NyBTYWx0ZWRfX/OBur3l2BmiA kpXPehBXXA2EdIRxmK9xiawBb6wdWKCK0ZAh3fvCbM9s0cFBYi6tXdg/NqMBjOZQ5sjCxNZ6KkZ JCSjs6szE3rlkB/CiKvxFw99zNKXsXw= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-11_05,2026-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 clxscore=1015 bulkscore=0 impostorscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611110077 On Mon, Aug 24, 2026 at 01:17:37AM +0530, Abhinaba Rakshit wrote: > Introduce support for dynamic clock scaling of the ICE (Inline Crypto Engine) > using the OPP framework. During ICE device probe, the driver now attempts to > parse an optional OPP table from the ICE-specific device tree node for > DVFS-aware operations. API qcom_ice_scale_clk is exposed by ICE driver > and is invoked by UFS host controller driver in response to clock scaling > requests, ensuring coordination between ICE and host controller. > > For MMC controllers that do not support clock scaling, the ICE clock frequency > is kept aligned with the MMC controller’s clock rate (TURBO) to ensure > consistent operation. > > Dynamic clock scaling based on OPP tables enables better power-performance > trade-offs. By adjusting ICE clock frequencies according to workload and power > constraints, the system can achieve higher throughput when needed and > reduce power consumption during idle or low-load conditions. > > The OPP table remains optional, absence of the table will not cause > probe failure. However, in the absence of an OPP table, ICE clocks will > remain at their default rates, which may limit performance under > high-load scenarios or prevent performance optimizations during idle periods. > > Testing: > * dtbs_check > * Validated on Rb3Gen2, qcs8300-ride-sx and LeMans-evk > > Merge Order and Dependencies > ============================ > > Patch 2 is dependent on patch 1 for the qcom_ice_scale_clk() API to be available. > Patch 3 is dependent on patch 1 for the qcom_ice_scale_clk() API to be available. > > Due to dependency, all patches should go through Qcom SoC tree. > > This patchset supersedes earlier ICE clock scaling series (v1–v11) with updated dependencies. > Hence, this patchset also *Depends-On* the following patchseries: > > [1] Enable sdhc inline crypto engine for kodiak and monaco > https://lore.kernel.org/all/20260707-ice_emmc_support-v9-0-701c86f3c25b@oss.qualcomm.com/ > > Similar to patchset v11, patchset v12 is rebased on top of latest changes picked onto linux-next. > > Signed-off-by: Abhinaba Rakshit Hello Bjorn, This series has been posted for a while now and I don't see any outstanding review comments on it. Could you pick it up into your tree for next RC? Although the series reads as a feature enablement, it's addressing a real regression: on several chipsets, turning on the Inline Crypto Engine today causes a significant storage throughput drop without this series applied. For example: Without ICE: Sequential Read: 220 MB/s, Sequential Write: 310 MB/s With ICE enabled: Sequential Read: 143.717 MB/s, Sequential Write: 126.762 MB/s That's roughly a 35-60% drop in throughput (averaging ~50%). This series is what makes ICE usable without that penalty, so merging it would let anyone enabling ICE today actually get the performance it's meant to provide. Abhinaba Rakshit