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Thu, 12 Nov 2026 07:21:07 -0700 Received: from MON-LT-C78453.mchp-main.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58 via Frontend Transport; Thu, 12 Nov 2026 07:21:06 -0700 Date: Thu, 12 Nov 2026 09:21:05 -0500 From: Charles Perry To: Vineeth Karumanchi CC: Charles Perry , , , , , , , , , , , Subject: Re: [PATCH net-next v2 4/4] net: macb: Add TSN CBS TC offload support Message-ID: References: <20260909142056.1433875-1-vineeth.karumanchi@amd.com> <20260909142056.1433875-5-vineeth.karumanchi@amd.com> <14e6511e-3878-4e14-8c25-7db5c179db8e@amd.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <14e6511e-3878-4e14-8c25-7db5c179db8e@amd.com> On Thu, Nov 12, 2026 at 03:39:26PM +0530, Vineeth Karumanchi wrote: > Hi Charles, > > On 11/10/2026 8:29 PM, Charles Perry wrote: > > Hello Vineeth, > > > > On Wed, Sep 09, 2026 at 07:50:56PM +0530, Vineeth Karumanchi wrote: > >> + > >> + /* qopt->idleslope is in kbps; convert to the units the hardware > >> + * register expects: > >> + * - High-speed GEM: fraction of port bandwidth, scaled to the full > >> + * 32-bit register range > >> + * - Standard MACB: the register counts bytes/sec in 1G (8-bit GMII) > >> + * mode and nibbles/sec in 10/100 (4-bit MII) mode, so scale kbps > >> + * by 1000/8 (125) or 1000/4 (250) respectively > >> + */ > >> + if (bp->caps & MACB_CAPS_HIGH_SPEED) > >> + idleslope = DIV_ROUND_UP_ULL((u64)qopt->idleslope * U32_MAX, speed_kbps); > >> + else > >> + idleslope = (u32)qopt->idleslope * (kset.base.speed >= 1000 ? > >> + MACB_CBS_PORT_RATE_1G : MACB_CBS_PORT_RATE_10_100M); > >> + > > > > PIC64-HPSC, which has MACB_CAPS_HIGH_SPEED, doesn't have the first idle > > slope calculation method which scales to the full 32 bits register range. > > It uses nibble/sec for 10/100M, byte/sec for 1G, 2.5bytes/sec for 2.5G, > > 5bytes/sec for 5G and 10bytes/sec for 10G. > > > > Is it possible that you have another design config bit for the "full 32 > > bits register range" method used here? > > > > The Cadence GEM revision `r1p14f2` in our implementation uses linear > scaling across the full 32-bit idleSlope register range, as confirmed by > Cadence support. However, the register description specifies only the > second, speed-dependent formula, which does not match our observations. Ok, on my side, Arya (cced) who did the testing confirmed that the measured bandwidth is off with the 32-bits method. I think he tested at 1G. > > I couldn’t find a configuration bit that distinguishes between these > behaviors. Which Cadence IP revision is used in PIC64-HPSC? r1p14f2a The revision register reads: 0x220c010e DCFG1: 08108510 DCFG2: 7af13fff DCFG3: 24000000 DCFG4: 00000000 DCFG5: 502e7344 DCFG6: 0f9300fe DCFG7: 00000000 DCFG8: 10100820 DCFG9: 00000000 DCFG10: 24454444 DCFG11: 000000f6 DCFG12: 37770101 DCFG13: 00037640 > > I can follow up with Cadence support to determine how software can > identify which encoding applies. Cool! Thank you. > > Thanks, > -- > 🙏 Vineeth > -- Thanks, Charles