Hi all,

Today's linux-next merge of the clk tree got a conflict in:

  drivers/clk/socfpga/clk-s10.c

between commit:

  4dd10fbbeb9c3 ("treewide: Convert devm_kmalloc() family to the devm_kmalloc_obj() family")

from the origin tree and commit:

  51805c5218c7e ("clk: socfpga: stratix10: register the SP timer clocks early")

from the clk tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

diff --cc drivers/clk/socfpga/clk-s10.c
index aad66f8d069d2,1976789b5166a..0000000000000
--- a/drivers/clk/socfpga/clk-s10.c
+++ b/drivers/clk/socfpga/clk-s10.c
@@@ -382,33 -397,112 +397,111 @@@ static int s10_clk_register_pll(const s
  	return 0;
  }
  
- static int s10_clkmgr_init(struct platform_device *pdev)
+ static struct stratix10_clock_data *s10_clk_data;
+ 
+ static struct stratix10_clock_data *s10_clk_data_alloc(void __iomem *base)
  {
- 	struct device_node *np = pdev->dev.of_node;
- 	struct device *dev = &pdev->dev;
  	struct stratix10_clock_data *clk_data;
- 	void __iomem *base;
- 	int i, num_clks;
+ 	int i;
  
- 	base = devm_platform_ioremap_resource(pdev, 0);
- 	if (IS_ERR(base)) {
- 		pr_err("%s: failed to map clock registers\n", __func__);
- 		return PTR_ERR(base);
- 	}
- 
- 	num_clks = STRATIX10_NUM_CLKS;
- 	clk_data = devm_kzalloc_flex(dev, *clk_data, clk_data.hws, num_clks);
 -	clk_data = kzalloc(struct_size(clk_data, clk_data.hws, STRATIX10_NUM_CLKS),
 -			   GFP_KERNEL);
++	clk_data = kzalloc_flex(*clk_data, clk_data.hws, STRATIX10_NUM_CLKS);
  	if (!clk_data)
- 		return -ENOMEM;
+ 		return NULL;
  
  	clk_data->base = base;
- 	clk_data->clk_data.num = num_clks;
+ 	clk_data->clk_data.num = STRATIX10_NUM_CLKS;
  
- 	for (i = 0; i < num_clks; i++)
- 		clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
+ 	for (i = 0; i < STRATIX10_NUM_CLKS; i++)
+ 		clk_data->clk_data.hws[i] = ERR_PTR(-EPROBE_DEFER);
  
+ 	return clk_data;
+ }
+ 
+ static void s10_clk_register_early(struct stratix10_clock_data *clk_data)
+ {
  	s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data);
  
+ 	s10_clk_register_c_perip(s10_early_perip_c_clks,
+ 				 ARRAY_SIZE(s10_early_perip_c_clks), clk_data);
+ 
+ 	s10_clk_register_cnt_perip(s10_early_perip_cnt_clks,
+ 				   ARRAY_SIZE(s10_early_perip_cnt_clks),
+ 				   clk_data);
+ 
+ 	s10_clk_register_gate(s10_early_gate_clks,
+ 			      ARRAY_SIZE(s10_early_gate_clks), clk_data);
+ }
+ 
+ /*
+  * The registered clocks keep using the mapping and clk_data, so neither is
+  * released once the early clocks have been registered.
+  */
+ static int s10_clkmgr_setup(struct device_node *np)
+ {
+ 	struct stratix10_clock_data *clk_data;
+ 	void __iomem *base;
+ 
+ 	base = of_iomap(np, 0);
+ 	if (!base) {
+ 		pr_err("%s: failed to map clock registers\n", __func__);
+ 		return -ENOMEM;
+ 	}
+ 
+ 	clk_data = s10_clk_data_alloc(base);
+ 	if (!clk_data) {
+ 		iounmap(base);
+ 		return -ENOMEM;
+ 	}
+ 
+ 	s10_clk_register_early(clk_data);
+ 	s10_clk_data = clk_data;
+ 
+ 	return 0;
+ }
+ 
+ static int s10_clkmgr_add_provider(struct device_node *np)
+ {
+ 	static bool added;
+ 	int ret;
+ 
+ 	if (added)
+ 		return 0;
+ 
+ 	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
+ 				     &s10_clk_data->clk_data);
+ 	if (ret)
+ 		return ret;
+ 
+ 	added = true;
+ 
+ 	return 0;
+ }
+ 
+ static void __init s10_clkmgr_early_init(struct device_node *np)
+ {
+ 	if (s10_clkmgr_setup(np))
+ 		return;
+ 
+ 	if (s10_clkmgr_add_provider(np))
+ 		pr_err("%s: failed to add clock provider\n", __func__);
+ }
+ 
+ CLK_OF_DECLARE_DRIVER(stratix10_clkmgr, "intel,stratix10-clkmgr",
+ 		      s10_clkmgr_early_init);
+ 
+ static int s10_clkmgr_init(struct platform_device *pdev)
+ {
+ 	struct stratix10_clock_data *clk_data;
+ 	int i, ret;
+ 
+ 	if (!s10_clk_data) {
+ 		ret = s10_clkmgr_setup(pdev->dev.of_node);
+ 		if (ret)
+ 			return ret;
+ 	}
+ 
+ 	clk_data = s10_clk_data;
+ 
  	s10_clk_register_c_perip(s10_main_perip_c_clks,
  				 ARRAY_SIZE(s10_main_perip_c_clks), clk_data);