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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-379569b8389sm20332733eec.25.2026.11.13.20.28.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Nov 2026 20:28:12 -0800 (PST) Date: Sat, 14 Nov 2026 12:28:06 +0800 From: Shawn Guo To: Anurag Pateriya Cc: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jingyi Wang , linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bibek Kumar Patro Subject: Re: [PATCH RFC 2/2] remoteproc: qcom_q6v5_pas: map SOCCP carveout privileged-only Message-ID: References: <20261113-nord_embedded_el2-v1-0-48f717e97066@oss.qualcomm.com> <20261113-nord_embedded_el2-v1-2-48f717e97066@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261113-nord_embedded_el2-v1-2-48f717e97066@oss.qualcomm.com> X-Proofpoint-GUID: MlBa_VeKwDtUEIyvKpWHniiVLZ0QGryV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTE0MDAxNyBTYWx0ZWRfX2ddfLa2lPVvr GvI85gTNV/n8eNH4UW7wabGiqY0+gAgOJJ+xomjyE1HXM+gUitXyUP0g4RJe0xa/jQJOdAhzYeK jm4ndNb0rPm+SCUWLkFak+IrQjzVIQL9f5j5hkHUZIf3bPBBNr5e/ieSi6vfeqJlfb0kBU0v6QD WdlnvmdMkl9/ddfs1ceu7L2LR+dafom4rrqrH6FrQrnkFbGhWBzBado/NoBUJaX/CmrZ1rz64HS arKLgNhYMOfz6yUJicmX8gUUS0o9pyq3YtvsaNHA4nESOjzVQmUnsMuGpvQxH/9dy13krNxFNQL DSIxtMYQMBnUKAKJ1Nun3FHLIY901Hr68EDgXTrRS+NBcQNjw82Taijx1YYcXAy1f3LYoXW8usv fLURWu0R6jJRMNzavlxxMIQHytfwV4lYTjch5wOk850VcubG7wwPjwouvmx0yzCaA/kU3mumRgX SFYvun5w4ycJN2fnFmw== X-Proofpoint-Spam-Info: AW1haW4tMjYxMTE0MDAxNyBTYWx0ZWRfXzejCZEggVl+r ZGmCOyTgKiLFFb2SrdWmv9jUrQrkhIzyHeAEPDX6DSW2tD8w2DdcDfZJKGmrk5NHTxSA5g9YrWR z8aXenPLS/BWv3pgg6LPKSqBEywm3cU= X-Proofpoint-ORIG-GUID: MlBa_VeKwDtUEIyvKpWHniiVLZ0QGryV X-Authority-Analysis: v=2.4 cv=ecmo7LEH c=1 sm=1 tr=0 ts=6af7e35e cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=kj9zAlcOel0A:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=d2ahPazU6wztV3fc8WMA:9 a=CjuIK1q_8ugA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-14_01,2026-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 spamscore=0 bulkscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611140017 On Fri, Nov 13, 2026 at 05:54:13PM +0530, Anurag Pateriya wrote: > From: Bibek Kumar Patro > > SOCCP is a RISC-V core whose instruction fetches go through the > SMMU in privilege mode > > The memory region is mapped with IOMMU_READ | IOMMU_WRITE, which results > in permission fault when SOCCP fetches instruction, append IOMMU_PRIV to > mapping to allow it to fetch instructions. This says what fails and what makes it go away, but not why. A reader can't tell from this why an RW mapping is fine for a data access but faults on an instruction fetch, or why IOMMU_PRIV fixes it. As I understand it, the chain is: - Without IOMMU_PRIV, io-pgtable-arm sets AP[1] in the stage-1 PTE, so the carveout ends up AP[2:1] = 0b01, i.e. writable at the unprivileged level. - In the VMSAv8-64 stage-1 permission model, memory writable at the unprivileged level is implicitly privileged-execute-never, regardless of PXN. - SoCCP fetches arrive as privileged instruction transactions, so the first fetch takes a stage-1 permission fault (FSR.PF, FSYNR0.IND=1). - IOMMU_PRIV clears AP[1] (AP[2:1] = 0b00, privileged RW only), which removes the implicit PXN. Something along these lines: On Nord, when Linux runs at EL2 it owns the SoCCP stream and the remoteproc core maps the firmware carveout through a stage-1 SMMU context bank. qcom_pas_map_carveout() uses IOMMU_READ | IOMMU_WRITE without IOMMU_PRIV, so io-pgtable-arm builds stage-1 PTEs with AP[2:1] = 0b01: read/write at both privileged and unprivileged level. SoCCP is a RISC-V core whose instruction fetches reach the SMMU as privileged transactions. In the VMSAv8-64 stage-1 permission model, memory that is writable at the unprivileged level is implicitly privileged-execute-never, regardless of the PXN bit in the PTE. The first SoCCP instruction fetch after PAS authentication therefore takes a stage-1 permission fault (FSR.PF, FSYNR0.IND=1). Map the SoCCP carveout with IOMMU_PRIV, so the stage-1 PTEs are privileged read/write only (AP[2:1] = 0b00). This removes the implicit privileged-execute-never and lets SoCCP fetch from the carveout. Other PIL subsystems (e.g. Hexagon Q6) are not affected as their instruction fetches do not go through the SMMU in privileged mode. Another nit: please use SoCCP (instead of SOCCP) everywhere, e.g. patch subject, for sake of consistency. Shawn