From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Cc: Konrad Dybcio <konradybcio@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Kees Cook <kees@kernel.org>,
"Gustavo A. R. Silva" <gustavoars@kernel.org>,
Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Dmitry Baryshkov <lumag@kernel.org>,
Marijn Suijten <marijn.suijten@somainline.org>,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-hardening@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org
Subject: Re: [PATCH 0/4] Retrieve information about DDR from SMEM
Date: Fri, 11 Apr 2025 12:03:03 +0200 [thread overview]
Message-ID: <b04464b6-2ad9-4866-88e9-437e96645726@oss.qualcomm.com> (raw)
In-Reply-To: <CAO9ioeUeNeSxz7ADZ-BbJbhEKkszVS+SmbqaZCgTpL=csak=hg@mail.gmail.com>
On 4/11/25 11:57 AM, Dmitry Baryshkov wrote:
> On Fri, 11 Apr 2025 at 12:49, Konrad Dybcio
> <konrad.dybcio@oss.qualcomm.com> wrote:
>>
>> On 4/9/25 5:49 PM, Konrad Dybcio wrote:
>>> On 4/9/25 5:44 PM, Dmitry Baryshkov wrote:
>>>> On 09/04/2025 17:47, Konrad Dybcio wrote:
>>>>> SMEM allows the OS to retrieve information about the DDR memory.
>>>>> Among that information, is a semi-magic value called 'HBB', or Highest
>>>>> Bank address Bit, which multimedia drivers (for hardware like Adreno
>>>>> and MDSS) must retrieve in order to program the IP blocks correctly.
>>>>>
>>>>> This series introduces an API to retrieve that value, uses it in the
>>>>> aforementioned programming sequences and exposes available DDR
>>>>> frequencies in debugfs (to e.g. pass to aoss_qmp debugfs). More
>>>>> information can be exposed in the future, as needed.
>>>>
>>>> I know that for some platforms HBB differs between GPU and DPU (as it's being programmed currently). Is there a way to check, which values are we going to program:
>>>>
>>>> - SM6115, SM6350, SM6375 (13 vs 14)
>>
>> SM6350 has INFO_V3
>> SM6375 has INFO_V3_WITH_14_FREQS
>
> I'm not completely sure what you mean here. I pointed out that these
> platforms disagreed upon the HBB value between the DPU/msm_mdss.c and
> a6xx_gpu.c.
> In some cases (a610/SM6115 and a619/SM6350) that was intentional to
> fix screen corruption issues. I don't remember if it was the case for
> QCM2290 or not.
As I said below, I couldn't get a good answer yet, as the magic value
is not provided explicitly and I'll hopefully be able to derive it from
the available data
Konrad
>
>>
>>>> - SC8180X (15 vs 16)
>>
>> So I overlooked the fact that DDR info v3 (e.g. on 8180) doesn't provide
>> the HBB value.. Need to add some more sanity checks there.
>>
>> Maybe I can think up some fallback logic based on the DDR type reported.
>>
>>>> - QCM2290 (14 vs 15)
>>
>> I don't have one on hand, could you please give it a go on your RB1?
>> I would assume both it and SM6115 also provide v3 though..
>>
>> Konrad
>
>
>
next prev parent reply other threads:[~2025-04-11 10:03 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-09 14:47 Konrad Dybcio
2025-04-09 14:47 ` [PATCH 1/4] soc: qcom: Expose DDR data " Konrad Dybcio
2025-04-10 2:21 ` Bjorn Andersson
2025-04-09 14:47 ` [PATCH 2/4] drm/msm/a5xx: Get HBB dynamically, if available Konrad Dybcio
2025-04-09 14:47 ` [PATCH 3/4] drm/msm/a6xx: " Konrad Dybcio
2025-04-09 15:12 ` Connor Abbott
2025-04-09 15:22 ` Konrad Dybcio
2025-04-09 15:30 ` Connor Abbott
2025-04-09 15:40 ` Konrad Dybcio
2025-04-09 15:44 ` Connor Abbott
2025-04-09 15:46 ` Konrad Dybcio
2025-04-09 14:47 ` [PATCH 4/4] drm/msm/mdss: " Konrad Dybcio
2025-04-09 15:44 ` [PATCH 0/4] Retrieve information about DDR from SMEM Dmitry Baryshkov
2025-04-09 15:49 ` Konrad Dybcio
2025-04-11 9:48 ` Konrad Dybcio
2025-04-11 9:57 ` Dmitry Baryshkov
2025-04-11 10:03 ` Konrad Dybcio [this message]
2025-04-11 10:50 ` Dmitry Baryshkov
2025-04-11 10:52 ` Konrad Dybcio
2025-04-14 12:28 ` Dmitry Baryshkov
2025-04-14 13:06 ` Konrad Dybcio
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