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Tue, 10 Nov 2020 23:59:43 -0800 Envelope-to: git@xilinx.com, michal.simek@xilinx.com, marex@denx.de, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ulf.hansson@linaro.org, adrian.hunter@intel.com Received: from [172.30.17.110] (port=60358) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1kcl2c-0006P2-S2; Tue, 10 Nov 2020 23:59:43 -0800 Subject: Re: [PATCH] mmc: sdhci-of-arasan: Allow configuring zero tap values To: Manish Narani , , , CC: , , , , Sai Krishna Potthuri , Marek Vasut References: <1605030122-52196-1-git-send-email-manish.narani@xilinx.com> From: Michal Simek Message-ID: Date: Wed, 11 Nov 2020 08:59:39 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.4.2 MIME-Version: 1.0 In-Reply-To: <1605030122-52196-1-git-send-email-manish.narani@xilinx.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4095f067-f089-40de-588e-08d88617c377 X-MS-TrafficTypeDiagnostic: DM6PR02MB5130: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:6430; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2020 07:59:49.4044 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4095f067-f089-40de-588e-08d88617c377 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT039.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB5130 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org +Marek On 10. 11. 20 18:42, Manish Narani wrote: > Allow configuring the Output and Input tap values with zero to avoid > failures in some cases (one of them is SD boot mode) where the output > and input tap values may be already set to non-zero. > > Signed-off-by: Sai Krishna Potthuri > Signed-off-by: Manish Narani > --- > drivers/mmc/host/sdhci-of-arasan.c | 40 ++++++------------------------ > 1 file changed, 8 insertions(+), 32 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c > index 829ccef87426..100621e55427 100644 > --- a/drivers/mmc/host/sdhci-of-arasan.c > +++ b/drivers/mmc/host/sdhci-of-arasan.c > @@ -600,14 +600,8 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees) > u8 tap_delay, tap_max = 0; > int ret; > > - /* > - * This is applicable for SDHCI_SPEC_300 and above > - * ZynqMP does not set phase for <=25MHz clock. > - * If degrees is zero, no need to do anything. > - */ > - if (host->version < SDHCI_SPEC_300 || > - host->timing == MMC_TIMING_LEGACY || > - host->timing == MMC_TIMING_UHS_SDR12 || !degrees) > + /* This is applicable for SDHCI_SPEC_300 and above */ > + if (host->version < SDHCI_SPEC_300) > return 0; > > switch (host->timing) { > @@ -668,14 +662,8 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees) > u8 tap_delay, tap_max = 0; > int ret; > > - /* > - * This is applicable for SDHCI_SPEC_300 and above > - * ZynqMP does not set phase for <=25MHz clock. > - * If degrees is zero, no need to do anything. > - */ > - if (host->version < SDHCI_SPEC_300 || > - host->timing == MMC_TIMING_LEGACY || > - host->timing == MMC_TIMING_UHS_SDR12 || !degrees) > + /* This is applicable for SDHCI_SPEC_300 and above */ > + if (host->version < SDHCI_SPEC_300) > return 0; > > switch (host->timing) { > @@ -733,14 +721,8 @@ static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees) > struct sdhci_host *host = sdhci_arasan->host; > u8 tap_delay, tap_max = 0; > > - /* > - * This is applicable for SDHCI_SPEC_300 and above > - * Versal does not set phase for <=25MHz clock. > - * If degrees is zero, no need to do anything. > - */ > - if (host->version < SDHCI_SPEC_300 || > - host->timing == MMC_TIMING_LEGACY || > - host->timing == MMC_TIMING_UHS_SDR12 || !degrees) > + /* This is applicable for SDHCI_SPEC_300 and above */ > + if (host->version < SDHCI_SPEC_300) > return 0; > > switch (host->timing) { > @@ -804,14 +786,8 @@ static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees) > struct sdhci_host *host = sdhci_arasan->host; > u8 tap_delay, tap_max = 0; > > - /* > - * This is applicable for SDHCI_SPEC_300 and above > - * Versal does not set phase for <=25MHz clock. > - * If degrees is zero, no need to do anything. > - */ > - if (host->version < SDHCI_SPEC_300 || > - host->timing == MMC_TIMING_LEGACY || > - host->timing == MMC_TIMING_UHS_SDR12 || !degrees) > + /* This is applicable for SDHCI_SPEC_300 and above */ > + if (host->version < SDHCI_SPEC_300) > return 0; > > switch (host->timing) { >