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From: Geraldo Nascimento <geraldogabriel@gmail.com>
To: linux-rockchip@lists.infradead.org
Cc: "Shawn Lin" <shawn.lin@rock-chips.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Heiko Stuebner" <heiko@sntech.de>,
	linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Johan Jonker" <jbx6244@gmail.com>,
	"Geraldo Nascimento" <geraldogabriel@gmail.com>,
	"Dragan Simic" <dsimic@manjaro.org>
Subject: [PATCH 2/3] PCI: rockchip-host: comment danger of 5.0 GT/s speed
Date: Sat, 15 Nov 2025 06:10:36 -0300	[thread overview]
Message-ID: <b04ed0deb42c914847dd28233010f9573d6b5902.1763197368.git.geraldogabriel@gmail.com> (raw)
In-Reply-To: <cover.1763197368.git.geraldogabriel@gmail.com>

According to Rockchip sources, there is grave danger in enabling 5.0
GT/s speed for this core. Add a comment documenting that danger and
discouraging end-users from forcing higher speed through DT changes.

Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock-chips.com/
Reported-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>
---
 drivers/pci/controller/pcie-rockchip-host.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
index ee1822ca01db..7e6ff76466b7 100644
--- a/drivers/pci/controller/pcie-rockchip-host.c
+++ b/drivers/pci/controller/pcie-rockchip-host.c
@@ -332,6 +332,11 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
 		/*
 		 * Enable retrain for gen2. This should be configured only after
 		 * gen1 finished.
+		 *
+		 * According to Rockchip this path is dangerous and may lead to
+		 * catastrophic failure. Even if the odds are small, users are
+		 * still discouraged to engage the corresponding DT option.
+		 *
 		 */
 		status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2);
 		status &= ~PCI_EXP_LNKCTL2_TLS;
-- 
2.49.0


  parent reply	other threads:[~2025-11-15  9:10 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-15  9:10 [PATCH 0/3] PCI: rockchip: 5.0 GT/s speed may be dangerous Geraldo Nascimento
2025-11-15  9:10 ` [PATCH 1/3] PCI: rockchip: warn of danger of 5.0 GT/s speeds Geraldo Nascimento
2025-11-15  9:24   ` Dragan Simic
2025-11-15  9:49     ` Geraldo Nascimento
2025-11-15  9:10 ` Geraldo Nascimento [this message]
2025-11-15  9:30   ` [PATCH 2/3] PCI: rockchip-host: comment danger of 5.0 GT/s speed Dragan Simic
2025-11-15  9:51     ` Geraldo Nascimento
2025-11-15 10:01       ` Dragan Simic
2025-11-15 10:04         ` Geraldo Nascimento
2025-11-15 10:09           ` Dragan Simic
2025-11-15 10:11             ` Geraldo Nascimento
2025-11-15  9:10 ` [PATCH 3/3] arm64: dts: rockchip: drop max-link-speed = <2> in helios64 PCIe Geraldo Nascimento
2025-11-15  9:36   ` Dragan Simic
2025-11-15  9:42     ` Dragan Simic
2025-11-15  9:55       ` Geraldo Nascimento
2025-11-15 10:03         ` Dragan Simic
2025-11-15  9:53     ` Geraldo Nascimento
2025-11-17  3:42 ` [PATCH 0/3] PCI: rockchip: 5.0 GT/s speed may be dangerous Shawn Lin
2025-11-17  3:57   ` Dragan Simic
2025-11-17  7:02     ` Geraldo Nascimento
2025-11-17 15:59       ` Dragan Simic

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