From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 376AD29E0F0 for ; Thu, 17 Jul 2025 13:05:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752757553; cv=none; b=KbX6eXnKSr2OD91rIfQkt2ZjlR+HhsvsjNLdihB3Kewm95koxLR2TyhOo/5NpPVHIeMMf9IJY6jrRDVWxLIIWu3nSt2XVKhnNFJRg4Bu1rxqKq3HYoakPGzeERCTmDF3HrPYVJ1m+NfneWGFfK5e0+aoXGttHCw+N4hio2xi2M0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752757553; c=relaxed/simple; bh=NMLZnzlmIf/uA05C9mlTJs9/jHSpAuhCtMXcuVgxdPQ=; h=Message-ID:Date:MIME-Version:Subject:From:To:References: In-Reply-To:Content-Type; b=Jv9M5zhR9c+Tyqyt2rIVpbxAoW9gI2zgJxKWYd4aKTMC/kwfiEVHTCMQFS22ARDr9rpInu63xrF+5z6A8RzAoXQD3BqqEg9sKbPYnV6Wdd31MxFCal1w4d6HXGFtRrSnzRsJOrpgcld6WGwtpJVHlzX9CrSjus9eHIB6MG84iIY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ghiti.fr; spf=pass smtp.mailfrom=ghiti.fr; arc=none smtp.client-ip=217.70.183.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ghiti.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ghiti.fr Received: by mail.gandi.net (Postfix) with ESMTPSA id A208A441BF; Thu, 17 Jul 2025 13:05:45 +0000 (UTC) Message-ID: Date: Thu, 17 Jul 2025 15:05:44 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC 2/2] riscv: introduce percpu.h into include/asm From: Alexandre Ghiti To: Yunhui Cui , yury.norov@gmail.com, linux@rasmusvillemoes.dk, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, dennis@kernel.org, tj@kernel.org, cl@gentwo.org, linux-mm@kvack.org References: <20250618034328.21904-1-cuiyunhui@bytedance.com> <20250618034328.21904-2-cuiyunhui@bytedance.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeeffedrtdefgdeitdeihecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfitefpfffkpdcuggftfghnshhusghstghrihgsvgenuceurghilhhouhhtmecufedtudenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhepkfffgggfuffhvfhfjggtgfesthekredttddvjeenucfhrhhomheptehlvgigrghnughrvgcuifhhihhtihcuoegrlhgvgiesghhhihhtihdrfhhrqeenucggtffrrghtthgvrhhnpeeiudelveeghfevteefueejleejgfeiveduffdvueehveekhfehueefvdelgfffueenucfkphepudekhedrvddufedrudehgedrudehudenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepihhnvghtpedukeehrddvudefrdduheegrdduhedupdhhvghloheplgdutddrudegrddtrddufegnpdhmrghilhhfrhhomheprghlvgigsehghhhithhirdhfrhdpnhgspghrtghpthhtohepuddvpdhrtghpthhtoheptghuihihuhhnhhhuihessgihthgvuggrnhgtvgdrtghomhdprhgtphhtthhopeihuhhrhidrnhhorhhovhesghhmrghilhdrtghomhdprhgtphhtthhopehlihhnuhigsehrrghsmhhushhvihhllhgvmhhovghsrdgukhdprhgtphhtthhopehprghulhdrfigrlhhmshhlvgihsehsihhfihhvvgdrtghomhdprhgtphhtthhopehprghlmhgvrhesuggrsggsvghlthdrtghomhdprhgtphhtthhopegrohhusegvvggtshdrs ggvrhhkvghlvgihrdgvughupdhrtghpthhtoheplhhinhhugidqrhhishgtvheslhhishhtshdrihhnfhhrrgguvggrugdrohhrghdprhgtphhtthhopehlihhnuhigqdhkvghrnhgvlhesvhhgvghrrdhkvghrnhgvlhdrohhrgh X-GND-Sasl: alex@ghiti.fr On 7/17/25 15:04, Alexandre Ghiti wrote: > Hi Yunhui, > > On 6/18/25 05:43, Yunhui Cui wrote: >> Current percpu operations rely on generic implementations, where >> raw_local_irq_save() introduces substantial overhead. Optimization >> is achieved through atomic operations and preemption disabling. >> >> Signed-off-by: Yunhui Cui >> --- >>   arch/riscv/include/asm/percpu.h | 138 ++++++++++++++++++++++++++++++++ >>   1 file changed, 138 insertions(+) >>   create mode 100644 arch/riscv/include/asm/percpu.h >> >> diff --git a/arch/riscv/include/asm/percpu.h >> b/arch/riscv/include/asm/percpu.h >> new file mode 100644 >> index 0000000000000..423c0d01f874c >> --- /dev/null >> +++ b/arch/riscv/include/asm/percpu.h >> @@ -0,0 +1,138 @@ >> +/* SPDX-License-Identifier: GPL-2.0-only */ >> + >> +#ifndef __ASM_PERCPU_H >> +#define __ASM_PERCPU_H >> + >> +#include >> + >> +#define PERCPU_RW_OPS(sz)                        \ >> +static inline unsigned long __percpu_read_##sz(void *ptr)        \ >> +{                                    \ >> +    return READ_ONCE(*(u##sz *)ptr);                \ >> +}                                    \ >> +                                    \ >> +static inline void __percpu_write_##sz(void *ptr, unsigned long >> val)    \ >> +{                                    \ >> +    WRITE_ONCE(*(u##sz *)ptr, (u##sz)val);                \ >> +} >> + >> +#define __PERCPU_AMO_OP_CASE(sfx, name, sz, amo_insn)            \ >> +static inline void                            \ >> +__percpu_##name##_amo_case_##sz(void *ptr, unsigned long val)        \ >> +{                                    \ >> +    asm volatile (                            \ >> +    "amo" #amo_insn #sfx " zero, %[val], %[ptr]"            \ >> +    : [ptr] "+A" (*(u##sz *)ptr)                    \ >> +    : [val] "r" ((u##sz)(val))                    \ >> +    : "memory");                            \ >> +} >> + >> +#define __PERCPU_AMO_RET_OP_CASE(sfx, name, sz, amo_insn)        \ >> +static inline u##sz                            \ >> +__percpu_##name##_return_amo_case_##sz(void *ptr, unsigned long >> val)    \ >> +{                                    \ >> +    register u##sz ret;                        \ >> +                                    \ >> +    asm volatile (                            \ >> +    "amo" #amo_insn #sfx " %[ret], %[val], %[ptr]"            \ >> +    : [ptr] "+A" (*(u##sz *)ptr), [ret] "=r" (ret)            \ >> +    : [val] "r" ((u##sz)(val))                    \ >> +    : "memory");                            \ >> +                                    \ >> +    return ret + val;                        \ >> +} >> + >> +#define PERCPU_OP(name, amo_insn)                    \ >> +    __PERCPU_AMO_OP_CASE(.b, name, 8, amo_insn)            \ >> +    __PERCPU_AMO_OP_CASE(.h, name, 16, amo_insn)            \ >> +    __PERCPU_AMO_OP_CASE(.w, name, 32, amo_insn)            \ >> +    __PERCPU_AMO_OP_CASE(.d, name, 64, amo_insn)            \ >> + >> +#define PERCPU_RET_OP(name, amo_insn)                    \ >> +    __PERCPU_AMO_RET_OP_CASE(.b, name, 8, amo_insn) \ >> +    __PERCPU_AMO_RET_OP_CASE(.h, name, 16, amo_insn)        \ >> +    __PERCPU_AMO_RET_OP_CASE(.w, name, 32, amo_insn)        \ >> +    __PERCPU_AMO_RET_OP_CASE(.d, name, 64, amo_insn) >> + >> +PERCPU_RW_OPS(8) >> +PERCPU_RW_OPS(16) >> +PERCPU_RW_OPS(32) >> +PERCPU_RW_OPS(64) >> + >> +PERCPU_OP(add, add) >> +PERCPU_OP(andnot, and) >> +PERCPU_OP(or, or) >> +PERCPU_RET_OP(add, add) >> + >> +#undef PERCPU_RW_OPS >> +#undef __PERCPU_AMO_OP_CASE >> +#undef __PERCPU_AMO_RET_OP_CASE >> +#undef PERCPU_OP >> +#undef PERCPU_RET_OP >> + >> +#define _pcp_protect(op, pcp, ...)                    \ >> +({                                    \ >> +    preempt_disable_notrace();                    \ >> +    op(raw_cpu_ptr(&(pcp)), __VA_ARGS__);                \ >> +    preempt_enable_notrace();                    \ >> +}) >> + >> +#define _pcp_protect_return(op, pcp, args...)                \ >> +({                                    \ >> +    typeof(pcp) __retval;                        \ >> +    preempt_disable_notrace();                    \ >> +    __retval = (typeof(pcp))op(raw_cpu_ptr(&(pcp)), ##args);    \ >> +    preempt_enable_notrace();                    \ >> +    __retval;                            \ >> +}) >> + >> +#define this_cpu_read_1(pcp) _pcp_protect_return(__percpu_read_8, pcp) >> +#define this_cpu_read_2(pcp) _pcp_protect_return(__percpu_read_16, pcp) >> +#define this_cpu_read_4(pcp) _pcp_protect_return(__percpu_read_32, pcp) >> +#define this_cpu_read_8(pcp) _pcp_protect_return(__percpu_read_64, pcp) >> + >> +#define this_cpu_write_1(pcp, val) _pcp_protect(__percpu_write_8, >> pcp, (unsigned long)val) >> +#define this_cpu_write_2(pcp, val) _pcp_protect(__percpu_write_16, >> pcp, (unsigned long)val) >> +#define this_cpu_write_4(pcp, val) _pcp_protect(__percpu_write_32, >> pcp, (unsigned long)val) >> +#define this_cpu_write_8(pcp, val) _pcp_protect(__percpu_write_64, >> pcp, (unsigned long)val) >> + >> +#define this_cpu_add_1(pcp, val) >> _pcp_protect(__percpu_add_amo_case_8, pcp, val) >> +#define this_cpu_add_2(pcp, val) >> _pcp_protect(__percpu_add_amo_case_16, pcp, val) >> +#define this_cpu_add_4(pcp, val) >> _pcp_protect(__percpu_add_amo_case_32, pcp, val) >> +#define this_cpu_add_8(pcp, val) >> _pcp_protect(__percpu_add_amo_case_64, pcp, val) >> + >> +#define this_cpu_add_return_1(pcp, val)        \ >> +_pcp_protect_return(__percpu_add_return_amo_case_8, pcp, val) >> + >> +#define this_cpu_add_return_2(pcp, val)        \ >> +_pcp_protect_return(__percpu_add_return_amo_case_16, pcp, val) >> + >> +#define this_cpu_add_return_4(pcp, val)        \ >> +_pcp_protect_return(__percpu_add_return_amo_case_32, pcp, val) >> + >> +#define this_cpu_add_return_8(pcp, val)        \ >> +_pcp_protect_return(__percpu_add_return_amo_case_64, pcp, val) >> + >> +#define this_cpu_and_1(pcp, val) >> _pcp_protect(__percpu_andnot_amo_case_8, pcp, ~val) >> +#define this_cpu_and_2(pcp, val) >> _pcp_protect(__percpu_andnot_amo_case_16, pcp, ~val) >> +#define this_cpu_and_4(pcp, val) >> _pcp_protect(__percpu_andnot_amo_case_32, pcp, ~val) >> +#define this_cpu_and_8(pcp, val) >> _pcp_protect(__percpu_andnot_amo_case_64, pcp, ~val) > > > Why do we define __percpu_andnot based on amoand, and use > __percpu_andnot with ~val here? Can't we just define __percpu_and? > > >> + >> +#define this_cpu_or_1(pcp, val) _pcp_protect(__percpu_or_amo_case_8, >> pcp, val) >> +#define this_cpu_or_2(pcp, val) >> _pcp_protect(__percpu_or_amo_case_16, pcp, val) >> +#define this_cpu_or_4(pcp, val) >> _pcp_protect(__percpu_or_amo_case_32, pcp, val) >> +#define this_cpu_or_8(pcp, val) >> _pcp_protect(__percpu_or_amo_case_64, pcp, val) >> + >> +#define this_cpu_xchg_1(pcp, val) _pcp_protect_return(xchg_relaxed, >> pcp, val) >> +#define this_cpu_xchg_2(pcp, val) _pcp_protect_return(xchg_relaxed, >> pcp, val) >> +#define this_cpu_xchg_4(pcp, val) _pcp_protect_return(xchg_relaxed, >> pcp, val) >> +#define this_cpu_xchg_8(pcp, val) _pcp_protect_return(xchg_relaxed, >> pcp, val) >> + >> +#define this_cpu_cmpxchg_1(pcp, o, n) >> _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) >> +#define this_cpu_cmpxchg_2(pcp, o, n) >> _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) >> +#define this_cpu_cmpxchg_4(pcp, o, n) >> _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) >> +#define this_cpu_cmpxchg_8(pcp, o, n) >> _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) >> + >> +#include >> + >> +#endif /* __ASM_PERCPU_H */ > > > It all looks good to me, just one thing, can you also implement > this_cpu_cmpxchg64/128()? > One last thing sorry, can you add a cover letter too? Thanks! Alex > And since this is almost a copy/paste from arm64, either mention it at > the top of the file or (better) merge both implementations somewhere > to avoid redefining existing code :) But up to you. > > Reviewed-by: Alexandre Ghiti > > Thanks, > > Alex > > >