From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 32FC731355F for ; Mon, 5 Jan 2026 17:12:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767633146; cv=none; b=QVR3d5mhYqoC5HE5bKVOk6gO769QDX/uZcuT5nsVwATj9tY6dJW8sN8AJ4bqh1aX7QrAdYwpHF0wF5ovf8E2OMdIJ5zG40xdRjra3JpLegcxAjtK7EOzRZ9Lx+THc8ithm7IIWakqjXjTuHOyoYbQ1iMOzrWw9E1dsl91pII++g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767633146; c=relaxed/simple; bh=JwsLv7+EXeGpYiOpWB+zt7hEYD+hx3UOzh5sAtnnjUs=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=mtiZPhwC5wi3Zg7XvvsJbz7SDzvV6ERUUeOStm7Xl7hvFSISRny4h0F4G3TMq6FEy9Dw8TxngxCV1DNWdt4LxN9SRMmCWEIEFrC9ul+duvXuj4evJhbNVER8ZXO9Ss3wE0B0iT9RMpLtSQmh7GrMqYz7lu1BmvpFo4t2aoNrNws= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C3A7E339; Mon, 5 Jan 2026 09:12:17 -0800 (PST) Received: from [10.1.38.150] (XHFQ2J9959.cambridge.arm.com [10.1.38.150]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 595063F5A1; Mon, 5 Jan 2026 09:12:23 -0800 (PST) Message-ID: Date: Mon, 5 Jan 2026 17:12:22 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 02/13] arm64: mm: Introduce a C wrapper for by-range TLB invalidation Content-Language: en-GB To: Linu Cherian Cc: Will Deacon , Ard Biesheuvel , Catalin Marinas , Mark Rutland , Linus Torvalds , Oliver Upton , Marc Zyngier , Dev Jain , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20251216144601.2106412-1-ryan.roberts@arm.com> <20251216144601.2106412-3-ryan.roberts@arm.com> From: Ryan Roberts In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 05/01/2026 05:33, Linu Cherian wrote: > Ryan, > > On Tue, Dec 16, 2025 at 02:45:47PM +0000, Ryan Roberts wrote: >> As part of efforts to reduce our reliance on complex preprocessor macros >> for TLB invalidation routines, introduce a new C wrapper for by-range >> TLB invalidation which can be used instead of the __tlbi() macro and can >> additionally be called from C code. >> >> Each specific tlbi range op is implemented as a C function and the >> appropriate function pointer is passed to __tlbi_range(). Since >> everything is declared inline and is statically resolvable, the compiler >> will convert the indirect function call to a direct inline execution. >> >> Suggested-by: Linus Torvalds >> Signed-off-by: Ryan Roberts >> --- >> arch/arm64/include/asm/tlbflush.h | 33 ++++++++++++++++++++++++++++++- >> 1 file changed, 32 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h >> index 13a59cf28943..c5111d2afc66 100644 >> --- a/arch/arm64/include/asm/tlbflush.h >> +++ b/arch/arm64/include/asm/tlbflush.h >> @@ -459,6 +459,37 @@ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) >> * operations can only span an even number of pages. We save this for last to >> * ensure 64KB start alignment is maintained for the LPA2 case. >> */ >> +static __always_inline void rvae1is(u64 arg) >> +{ >> + __tlbi(rvae1is, arg); >> +} >> + >> +static __always_inline void rvale1(u64 arg) >> +{ >> + __tlbi(rvale1, arg); >> + __tlbi_user(rvale1, arg); > > Should this __tlbi_user be added as part of patch 3 ? Yes! I've screwed up a rebase since vale1/rvale1 only started being used in v6.19-rc1; I attempted to add it incrementally and have clearly screwed it up. I'll fix it all in the next rev. Thanks, Ryan > >> +} >> + >> +static __always_inline void rvale1is(u64 arg) >> +{ >> + __tlbi(rvale1is, arg); >> +} >> + >> +static __always_inline void rvaale1is(u64 arg) >> +{ >> + __tlbi(rvaale1is, arg); >> +} >> + >> +static __always_inline void ripas2e1is(u64 arg) >> +{ >> + __tlbi(ripas2e1is, arg); >> +} >> + >> +static __always_inline void __tlbi_range(tlbi_op op, u64 arg) >> +{ >> + op(arg); >> +} >> + >> #define __flush_tlb_range_op(op, start, pages, stride, \ >> asid, tlb_level, tlbi_user, lpa2) \ >> do { \ >> @@ -486,7 +517,7 @@ do { \ >> if (num >= 0) { \ >> addr = __TLBI_VADDR_RANGE(__flush_start >> shift, asid, \ >> scale, num, tlb_level); \ >> - __tlbi(r##op, addr); \ >> + __tlbi_range(r##op, addr); \ >> if (tlbi_user) \ >> __tlbi_user(r##op, addr); \ >> __flush_start += __TLBI_RANGE_PAGES(num, scale) << PAGE_SHIFT; \ >> -- >> 2.43.0 >>