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Thu, 24 Apr 2025 19:41:53 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 53OJfqkG002909 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Apr 2025 19:41:52 GMT Received: from [10.110.70.248] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 24 Apr 2025 12:41:51 -0700 Message-ID: Date: Thu, 24 Apr 2025 12:41:50 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/7] drm/msm/mdp4: register the LVDS PLL as a clock provider To: Dmitry Baryshkov CC: Dmitry Baryshkov , Rob Clark , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Bjorn Andersson" , Konrad Dybcio , , , , , , Konrad Dybcio References: <20250227-fd-mdp4-lvds-v3-0-c983788987ae@linaro.org> <20250227-fd-mdp4-lvds-v3-3-c983788987ae@linaro.org> <029f3bfb-a031-4dfe-a2b4-bc41a0da7772@quicinc.com> Content-Language: en-US From: Abhinav Kumar In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI0MDEzNyBTYWx0ZWRfX3P9lTmTh1nzA GZkD/jsp/3Z6etBOcdqVOaFYzwTlZN9w4KMyZeaSBHWmTfbwGznlPrJVnGNDdanLNgYXawWUgbS Y5yhCh8mVaUVzdMF86KExfivM9T3OgoYc/+MsD+R5IUKdO+SCF2p/bJrKxmPW+HG0Da/zLgjfHn tlnlYyq4LKjFO2DxBztzRZx2VKoKXjPNjmq+aFMe6xHJ0uZKHTzNQaAl/urZv15MAqnhCtcFrxs NaVzOBcIhETv7v+cyk3Ud0cYV66AX3N3MG9SjQjvmZcIaaRg7cn7dlbJ3ndU9u+Mln6l6G5K5Tu nsFDziZdirsluywhgsEY7LcTI8CenFPLCCdAW5YHCEri9Hc1oJTU6+FD2VrsJvieAhALpryYduR 27L5kFPN48/sVlleqz2AtO1HcjaA2GUeEf1XYX+5rMOSF9FLIK1jYp0cJ7GmNOtOkmLTyxVj X-Proofpoint-GUID: aTsTeaZslzfWCmtMOsf1f2bO3Chcbxq- X-Authority-Analysis: v=2.4 cv=ZuTtK87G c=1 sm=1 tr=0 ts=680a9401 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=3cKAJhnaDEdsQ5v88lUA:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: aTsTeaZslzfWCmtMOsf1f2bO3Chcbxq- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-24_08,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1011 impostorscore=0 bulkscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 mlxlogscore=999 priorityscore=1501 malwarescore=0 suspectscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504240137 On 4/24/2025 3:22 AM, Dmitry Baryshkov wrote: > On Wed, Apr 23, 2025 at 03:54:13PM -0700, Abhinav Kumar wrote: >> >> >> On 2/26/2025 6:25 PM, Dmitry Baryshkov wrote: >>> The LVDS/LCDC controller uses pixel clock coming from the multimedia >>> controller (mmcc) rather than using the PLL directly. Stop using LVDS >>> PLL directly and register it as a clock provider. Use lcdc_clk as a >>> pixel clock for the LCDC. >>> >>> Reviewed-by: Konrad Dybcio >>> Signed-off-by: Dmitry Baryshkov >>> --- >>> drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h | 2 +- >>> drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c | 8 +++++++- >>> drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c | 22 +++++++--------------- >>> 3 files changed, 15 insertions(+), 17 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h >>> index 142ccb68b435263f91ba1ab27676e426d43e5d84..b8bdc3712c73b14f3547dce3439a895e3d10f193 100644 >>> --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h >>> +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h >>> @@ -207,6 +207,6 @@ static inline struct drm_encoder *mdp4_dsi_encoder_init(struct drm_device *dev) >>> } >>> #endif >>> -struct clk *mpd4_lvds_pll_init(struct drm_device *dev); >>> +int mpd4_lvds_pll_init(struct drm_device *dev); >>> #endif /* __MDP4_KMS_H__ */ >>> diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c >>> index 8bbc7fb881d599e7d309cc61bda83697fecd253a..db93795916cdaa87ac8e61d3b44c2dadac10fd9e 100644 >>> --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c >>> +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c >>> @@ -381,7 +381,13 @@ struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_device *dev, >>> drm_encoder_helper_add(encoder, &mdp4_lcdc_encoder_helper_funcs); >>> /* TODO: do we need different pll in other cases? */ >>> - mdp4_lcdc_encoder->lcdc_clk = mpd4_lvds_pll_init(dev); >>> + ret = mpd4_lvds_pll_init(dev); >>> + if (ret) { >>> + DRM_DEV_ERROR(dev->dev, "failed to register LVDS PLL\n"); >>> + return ERR_PTR(ret); >>> + } >>> + >>> + mdp4_lcdc_encoder->lcdc_clk = devm_clk_get(dev->dev, "lcdc_clk"); >>> if (IS_ERR(mdp4_lcdc_encoder->lcdc_clk)) { >>> DRM_DEV_ERROR(dev->dev, "failed to get lvds_clk\n"); >>> return ERR_CAST(mdp4_lcdc_encoder->lcdc_clk); >> >> Change seems fine to me, one question on the order of changes, DT change has >> to be merged first otherwise it will fail here? > > It is already semi-broken, as just enabling the PLL is not enough. The > branch clocks in MMSS are to be toggled / manipulated. As such, it's > questionable if we need to coordinate or not. > Yes but wouldnt this cause mdp4_lcdc_encoder_init() failure which in turn will cause mdp4_kms_init() failure? So I thought that by merging the DTSI piece first this can be avoided. >> >> Will that be managed by co-ordinating with the DT maintainer? >> >