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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id d17-20020a05651233d100b0050e8e88b529sm2344518lfg.237.2024.01.23.10.09.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 23 Jan 2024 10:09:38 -0800 (PST) Message-ID: Date: Tue, 23 Jan 2024 19:09:37 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 05/11] arm64: dts: qcom: x1e80100: Add TCSR node Content-Language: en-US To: Abel Vesa , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240123-x1e80100-dts-missing-nodes-v4-0-072dc2f5c153@linaro.org> <20240123-x1e80100-dts-missing-nodes-v4-5-072dc2f5c153@linaro.org> From: Konrad Dybcio In-Reply-To: <20240123-x1e80100-dts-missing-nodes-v4-5-072dc2f5c153@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 1/23/24 12:01, Abel Vesa wrote: > Add the TCSR clock controller and halt register space node. > > Signed-off-by: Abel Vesa > --- The former - yes, the latter - ? Konrad > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index be69e71b7f53..2b6c55a486b2 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -2606,6 +2606,14 @@ tcsr_mutex: hwlock@1f40000 { > #hwlock-cells = <1>; > }; > > + tcsr: clock-controller@1fc0000 { > + compatible = "qcom,x1e80100-tcsr", "syscon"; > + reg = <0 0x01fc0000 0 0x30000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > gem_noc: interconnect@26400000 { > compatible = "qcom,x1e80100-gem-noc"; > reg = <0 0x26400000 0 0x311200>; >