From: <Conor.Dooley@microchip.com>
To: <heiko@sntech.de>, <paul.walmsley@sifive.com>,
<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>
Cc: <guoren@kernel.org>, <apatel@ventanamicro.com>,
<atishp@rivosinc.com>, <linux-riscv@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing
Date: Fri, 2 Sep 2022 09:31:27 +0000 [thread overview]
Message-ID: <b0f51962-4302-f005-8baa-ab41b81c0817@microchip.com> (raw)
In-Reply-To: <20220901222744.2210215-1-heiko@sntech.de>
On 01/09/2022 23:27, Heiko Stuebner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> This can also do without the ifdef and use IS_ENABLED instead and
> for better readability, getting rid of that switch also seems
> waranted.
The change itself looks great to me, but the commit message here
does not stand by itself - the "also" stuff reads a bit oddly.
How about:
---8<---
For better readability (and compile time coverage) use IS_ENABLED
instead of ifdef and drop the new unneeded switch statement.
---8<---
Call me biased, but I much prefer how this looks now...
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> arch/riscv/kernel/cpufeature.c | 13 +++++--------
> 1 file changed, 5 insertions(+), 8 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 553d755483ed..764ea220161f 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void)
> #ifdef CONFIG_RISCV_ALTERNATIVE
> static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
> {
> -#ifdef CONFIG_RISCV_ISA_SVPBMT
> - switch (stage) {
> - case RISCV_ALTERNATIVES_EARLY_BOOT:
> + if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT))
> return false;
> - default:
> - return riscv_isa_extension_available(NULL, SVPBMT);
> - }
> -#endif
>
> - return false;
> + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> + return false;
> +
> + return riscv_isa_extension_available(NULL, SVPBMT);
> }
>
> static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
> --
> 2.35.1
>
next prev parent reply other threads:[~2022-09-02 9:31 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-01 22:27 Heiko Stuebner
2022-09-01 22:27 ` [PATCH 2/4] riscv: drop some idefs from CMO initialization Heiko Stuebner
2022-09-02 1:05 ` Guo Ren
2022-09-02 9:34 ` Conor.Dooley
2022-09-02 9:49 ` Andrew Jones
2022-09-01 22:27 ` [PATCH 3/4] riscv: use BIT macros in t-head errata init Heiko Stuebner
2022-09-02 1:06 ` Guo Ren
2022-09-02 9:35 ` Conor.Dooley
2022-09-02 9:50 ` Andrew Jones
2022-09-01 22:27 ` [PATCH 4/4] riscv: check for kernel config option in t-head memory types errata Heiko Stuebner
2022-09-02 1:06 ` Guo Ren
2022-09-02 9:33 ` Conor.Dooley
2022-09-02 15:17 ` Heiko Stübner
2022-09-02 9:50 ` Andrew Jones
2022-09-02 1:07 ` [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing Guo Ren
2022-09-02 9:31 ` Conor.Dooley [this message]
2022-09-02 9:49 ` Andrew Jones
2022-09-02 15:12 ` Heiko Stübner
2022-09-02 15:26 ` Conor.Dooley
2022-09-02 15:34 ` Heiko Stübner
2022-09-02 19:29 ` Konstantin Ryabitsev
2022-09-02 9:50 ` Andrew Jones
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