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Mon, 08 Jun 2026 05:08:57 -0700 (PDT) X-Received: by 2002:a17:903:1ac5:b0:2c2:8659:da2c with SMTP id d9443c01a7336-2c28659dc9bmr20888535ad.14.1780920536563; Mon, 08 Jun 2026 05:08:56 -0700 (PDT) Received: from [10.206.105.200] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c1664a67b0sm183538985ad.80.2026.06.08.05.08.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Jun 2026 05:08:56 -0700 (PDT) Message-ID: Date: Mon, 8 Jun 2026 17:38:48 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v7 07/12] media: iris: Add power sequence for glymur Content-Language: en-US From: Vishnu Reddy To: Dmitry Baryshkov Cc: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanimir Varbanov , Bjorn Andersson , Konrad Dybcio , linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev, devicetree@vger.kernel.org References: <20260603-glymur-v7-0-afaa55d11fe0@oss.qualcomm.com> <20260603-glymur-v7-7-afaa55d11fe0@oss.qualcomm.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: 5HGHgkBGskWTY54XUpFpyxTeu254bZsI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA4MDExNSBTYWx0ZWRfX6a6mMdKOd6WQ zXwke6OOzivoae6Vbe0wDhhkroWxIa+7JC0RSEFWH1V/8s0mrPjIBr9f9PHPcXrkPfG2WAS4Hav u6lXDch/2Pf5+K7omSJKydG5djaeW95l0gtB93IyTrNb+4r76kXggs4bFxXJf3d9nffmBJcMJiy MZaawJkWuq8xrnpwzRMBP+a7nv+ubs68E2QquLWFRkvryv4u2Bf8bcfKbGTrSXvBL74PWjvedKz d7HYGA0xIwQGKewKHCThZCvpoAoGLwFrexsjIkYzePPqLmBL0l6+xxDqqmGbmfcDG9Yhq3LTbuY Gew6uEkh+zm1VFGQLjjahUhT+QtwrebxBc7faZKIYT0K86B/xvA9IeTnuTMDWTstc36+h32XFvq Db3WwmU9d7eYSc78fOHWXn5nNGZf6IIpUVmxhXVHYuma9Gh1SzHpzT1pq0LfChsxvoKJ2APdJ6U Pkf4/M8hgW6+2R5gn8g== X-Authority-Analysis: v=2.4 cv=XKAAjwhE c=1 sm=1 tr=0 ts=6a26b0da cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=zzk4QuvOVKE_xORUXiEA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: 5HGHgkBGskWTY54XUpFpyxTeu254bZsI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-08_03,2026-06-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 suspectscore=0 malwarescore=0 spamscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606080115 On 6/8/2026 11:09 AM, Vishnu Reddy wrote: > On 6/8/2026 3:17 AM, Dmitry Baryshkov wrote: >> On Wed, Jun 03, 2026 at 07:48:45PM +0530, Vishnu Reddy wrote: >>> Glymur platform has two video codec cores: vcodec0 and vcodec1. >>> >>> Both cores share a common clock source (video_cc_mvs0_clk_src) and the >>> same power rails. The clock dividers between the source and the branch >>> clocks are fixed. So when both cores are running, the source clock always >>> runs at the highest frequency requested by either core. >>> >>> Since both cores share the same power rails, the power corner cannot be >>> voted independently. Scaling one core's power corner up or down would >>> directly affect the other, leading to under or over-voting. >>> >>> For these reasons, both cores should voted the clock and power rail must >>> be based on the workload of both cores. >>> >>> Reviewed-by: Vikash Garodia >>> Signed-off-by: Vishnu Reddy >>> --- >>> drivers/media/platform/qcom/iris/iris_vpu3x.c | 111 ++++++++++++++++++++- >>> drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + >>> .../platform/qcom/iris/iris_vpu_register_defines.h | 10 ++ >>> 3 files changed, 117 insertions(+), 5 deletions(-) >>> >>> diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c >>> index 7cda94601555..f07eaf4b3be2 100644 >>> --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c >>> +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c >>> @@ -17,14 +17,14 @@ >>> #define NOC_HALT BIT(0) >>> #define AON_WRAPPER_SPARE (AON_BASE_OFFS + 0x28) >>> >>> -static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core) >>> +static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core, u32 pwr_status_bit) >>> { >>> u32 value, pwr_status; >>> >>> value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); >>> - pwr_status = value & BIT(1); >>> + pwr_status = value & pwr_status_bit; >>> >>> - return pwr_status ? false : true; >>> + return !pwr_status; >>> } >>> >>> static void iris_vpu3_power_off_hardware(struct iris_core *core) >>> @@ -32,7 +32,7 @@ static void iris_vpu3_power_off_hardware(struct iris_core *core) >>> u32 reg_val = 0, value, i; >>> int ret; >>> >>> - if (iris_vpu3x_hw_power_collapsed(core)) >>> + if (iris_vpu3x_hw_power_collapsed(core, VCODEC0_POWER_STATUS)) >>> goto disable_power; >>> >>> dev_err(core->dev, "video hw is power on\n"); >>> @@ -78,7 +78,7 @@ static void iris_vpu33_power_off_hardware(struct iris_core *core) >>> u32 count = 0; >>> int ret; >>> >>> - if (iris_vpu3x_hw_power_collapsed(core)) >>> + if (iris_vpu3x_hw_power_collapsed(core, VCODEC0_POWER_STATUS)) >>> goto disable_power; >>> >>> dev_err(core->dev, "video hw is power on\n"); >>> @@ -221,6 +221,98 @@ static void iris_vpu35_power_off_hw(struct iris_core *core) >>> iris_vpu33_power_off_hardware(core); >>> } >>> >>> +static void iris_vpu36_power_off_vcodec(struct iris_core *core, u32 core_id) >>> +{ >>> + u32 value, i; >>> + int ret; >>> + >>> + if (iris_vpu3x_hw_power_collapsed(core, >>> + core_id ? VCODEC1_POWER_STATUS : VCODEC0_POWER_STATUS)) >>> + goto disable_power; >>> + >>> + value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); >>> + if (value) >>> + writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); >>> + >>> + for (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) { >>> + ret = readl_poll_timeout(core->reg_base + (core_id ? VCODEC1_SS_IDLE_STATUSN : >>> + VCODEC_SS_IDLE_STATUSN) + 4 * i, value, >>> + value & DMA_NOC_IDLE, 2000, 20000); >> Unreadable. Extract register addresses to separate variables. > Ack > >>> + if (ret) >>> + goto disable_power; >>> + } >>> + >>> + writel(core_id ? REQ_VCODEC1_POWER_DOWN_PREP : REQ_POWER_DOWN_PREP, >>> + core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); >>> + ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS, value, >>> + value & (core_id ? NOC_LPI_VCODEC1_STATUS_DONE : >>> + NOC_LPI_STATUS_DONE), 2000, 20000); >>> + if (ret) >>> + goto disable_power; >>> + >>> + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); >>> + >>> + writel((core_id ? VCODEC1_BRIDGE_SW_RESET | VCODEC1_BRIDGE_HW_RESET_DISABLE : >>> + CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE), >>> + core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); >>> + writel(core_id ? VCODEC1_BRIDGE_HW_RESET_DISABLE : CORE_BRIDGE_HW_RESET_DISABLE, >>> + core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); >>> + writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); >>> + >>> +disable_power: >>> + dev_pm_genpd_set_hwmode(core->vcodec[core_id].dev, false); >>> + iris_disable_power_domain_and_clocks(core, &core->vcodec[core_id]); >>> +} >>> + >>> +static void iris_vpu36_power_off_hw(struct iris_core *core) >>> +{ >>> + u32 num_cores = max(core->iris_platform_data->num_cores, 1); >> Can we trust the patch authors that VPU3.6 hardware data will have at >> least 1 core? > On Glymur (VPU3.6), num_cores is 2. The max() guard is unnecessary. > Will access num_cores directly. > >>> + int i; >>> + >>> + for (i = 0; i < num_cores; i++) >>> + iris_vpu36_power_off_vcodec(core, i); >>> +} >>> + >>> #define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) >>> #define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) >> Lowercase hex. > Ack Just now I found that this change is not part of this series. Can I take this into separate post? >>> #define REQ_POWER_DOWN_PREP BIT(0) >>> +#define REQ_VCODEC1_POWER_DOWN_PREP BIT(1) >>>