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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODIxMDA3MyBTYWx0ZWRfX5Kq6d9pcWViS Mxw8M5/t03aHPkcxDYjAnPz9WY6b6+p8g3q/kpHRN1D92KUeYSUImYBG1ynId0DMLtG8JwQvp0I TNxAkcy8JcnATCP/NJD2eYgxqv2LlxSr7dRhw2Pgzv+7coS10dU9YPIzeJMbbjWSujLSQSir91d 62dqO7GTCnjZKRvWihWC/CW5pFPqqdyhBME9rgcKrzhBVthybqeLxROrMaxS6Opw5HRPP0zXvqt 04vwS10W1PeoJR9HTRFlx85pM4vMsHWaVe5EtuPeQryl2EpUSsKdFSuqWaSdKhGcbl0GqPUMfv3 bwKvuFwNxIdjkhteyrdo+wOlg5ZuyoXZfnYggaLQpHJy4RodAtS0jFq+utgHXYgFEpB25vmQXlB /jah+aKePvPrnHCI8ZVMrjassHRpglfn168kzzpW2nVLZH0eBBkREU1DUCVS56nbYYN9FaiT/rg tlhiwA1ceDE8O2Km/Lw== X-Proofpoint-Spam-Info: AW1haW4tMjYwODIxMDA3MyBTYWx0ZWRfX6/Meb2bsEsGC UMrZ1MD77zrGdyuUAKgW9rcpA4z06u5AbO5bw0V3fqnFJSTFNCkGYzQQHet/a5FyZ+UCPtorXC6 z3yaMinFSg+qpcdwNsB3JaiBaxildCA= X-Authority-Analysis: v=2.4 cv=DdQnbPtW c=1 sm=1 tr=0 ts=6a8820a4 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=01GmVmAJTjHGYBpbkKwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-ORIG-GUID: fqpJQ-MGmksqOrIroVPnAHyRjuJdLmJd X-Proofpoint-GUID: fqpJQ-MGmksqOrIroVPnAHyRjuJdLmJd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-21_03,2026-08-21_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 priorityscore=1501 phishscore=0 bulkscore=0 impostorscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608210073 Hi Mukesh On 20-08-2026 01:02, Mukesh Savaliya wrote: > > > On 8/18/2026 6:58 PM, Praveen Talari wrote: > [...] > >> +static int spi_geni_panic_notifier(struct notifier_block *nb, >> +                   unsigned long action, void *data) >> +{ >> +    struct spi_geni_master *mas = container_of(nb, struct >> spi_geni_master, panic_nb); >> +    struct spi_controller *spi = dev_get_drvdata(mas->dev); >> +    struct geni_se *se = &mas->se; >> +    u32 val; >> + >> +    if (!pm_runtime_active(mas->dev)) > > Not completely sure, but why not NOTIFY_DONE ? we haven't handled > anything here. My intention was to treat this as a successful no-op since no action is required when the device is runtime suspended. > >> +        return NOTIFY_OK; >> + >> +    if (mas->cur_xfer_mode == GENI_GPI_DMA) { >> +        dmaengine_terminate_async(mas->tx); >> +        dmaengine_terminate_async(mas->rx); >> +        return NOTIFY_OK; >> +    } >> + >> +    if (!(readl_relaxed(se->base + SE_GENI_STATUS) & >> M_GENI_CMD_ACTIVE)) > Shouldn't this be under FIFO mode check  ? As i can see SE DMA mode > and GPI mode conditions present but not for FIFO. This code path is shared between FIFO and SE_DMA modes. The DMA reset sequence below is only required when the transfer is operating in DMA mode. > >> +        return NOTIFY_OK; >> + >> +    if (!spi->target) { >> +        geni_se_cancel_m_cmd(se); >> +        if (!readl_poll_timeout_atomic(se->base + >> SE_GENI_M_IRQ_STATUS, val, >> +                           val & M_CMD_CANCEL_EN, 10, 50000)) { >> +            writel_relaxed(M_CMD_CANCEL_EN, se->base + >> SE_GENI_M_IRQ_CLEAR); >> +            return NOTIFY_OK; >> +        } >> +    } >> + >> +    geni_se_abort_m_cmd(se); > > why abort is done directly for target device and not for master ? > shouldn't be combined with cancel failure ? The target doesn't support cancel. >> +    if (!readl_poll_timeout_atomic(se->base + SE_GENI_M_IRQ_STATUS, >> val, >> +                       val & M_CMD_ABORT_EN, 10, 50000)) >> +        writel_relaxed(M_CMD_ABORT_EN, se->base + SE_GENI_M_IRQ_CLEAR); >> + >> +    if (mas->cur_xfer_mode == GENI_SE_DMA) { >> +        writel_relaxed(1, se->base + SE_DMA_TX_FSM_RST); >> +        readl_poll_timeout_atomic(se->base + SE_DMA_TX_IRQ_STAT, val, >> +                      val & TX_RESET_DONE, 10, 50000); >> +        writel_relaxed(val, se->base + SE_DMA_TX_IRQ_CLR); >> + >> +        writel_relaxed(1, se->base + SE_DMA_RX_FSM_RST); >> +        readl_poll_timeout_atomic(se->base + SE_DMA_RX_IRQ_STAT, val, >> +                      val & RX_RESET_DONE, 10, 50000); > May be good to declar macro for 10usec and 50msec ? Multiple places > it's being used.> +        writel_relaxed(val, se->base + > SE_DMA_RX_IRQ_CLR); Let me review and update. Thanks, Praveen Talari >> +    } >> + >> +    return NOTIFY_OK; >> +} >> +[...]