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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA2MDIwMiBTYWx0ZWRfX4Xk+sGsAsnXf xg9xCmdyV7jZClTJh+7HivLo5jHe1Zxh8YKDK/AKAF8IZcWpbCit9QyvO+ObEuLOGhtZz7tHsn9 4uOnX5YpI0zI6qMMh+qPANYPZcGla+2a0JF0r3rQDpalMTCnsK+8ZHcdEnvJLjHJh8/PvsKQyDk 5HS4lrA5+B+Y0LtNJucQy3SvP62oxdB3jGKY41zya4BRG7aahXcOACZVM305iyb3owRhTKy881C OJG3T/f8O59AFquqLA9NmLKV/DmwuRvWxXfnumdrhEienaUWVxECdmf9k9UAb5CyVfITB4V1o3J Ch4xXkDJAuKN1ph3Di08N9O5imGQGM1PfX3fCCDCM/3gqh2KlR36+lrWKNtV8zPHG78+W8jSX7S RngwXgKEbrZE7J9oIMXDlJrVINsw+XJs/7o8Du8Uh/oHJazyfDZHQerevdPlV55S+7kYCXF+Ru+ bS6cLMkwxIpOw5FyfDQ== X-Proofpoint-ORIG-GUID: GTZVhdDsee1VH3ZYeAXRWFplEytJ6CkM X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA2MDIwMiBTYWx0ZWRfX2lMqh0JTZIAo hGhPXHlg9YWX6TBAoR1VWWCcZP2eP2P6lbY+usZM7ed45vocRCGuB7fBgcEZNXxwj8umABZCnAo T7qNVBX5MGlSz7RtFZeYlRZM6sI+aUk= X-Proofpoint-GUID: GTZVhdDsee1VH3ZYeAXRWFplEytJ6CkM X-Authority-Analysis: v=2.4 cv=f9N4wuyM c=1 sm=1 tr=0 ts=6a4c0abb cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=fsdq8dFr2Uux402FS9br8A==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=ZaZH7ke036cbytEKeQwA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-06_02,2026-07-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 impostorscore=0 bulkscore=0 suspectscore=0 clxscore=1015 spamscore=0 phishscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607060202 On 7/6/2026 3:07 PM, Konrad Dybcio wrote: > On 7/5/26 10:00 AM, Akhil P Oommen wrote: >> Adreno 840 present in Kaanapali SoC is the second generation GPU in >> A8x family. It is based on the new slice architecture with 3 slices, >> higher GMEM/caches etc. >> >> There is some re-arrangement in the reglist to properly cover maximum >> register region. Other than this, the DT description is mostly similar >> to the existing chipsets except the OPP tables. >> >> Reviewed-by: Dmitry Baryshkov >> Signed-off-by: Akhil P Oommen >> --- > > [...] > >> + qcom,gmu = <&gmu>; >> + #cooling-cells = <2>; >> + >> + nvmem-cells = <&gpu_speed_bin>; >> + nvmem-cell-names = "speed_bin"; > > This looks good to me, but I thought that on a8x, we're supposed to use > the freq limiting register in CX_MISC - is either of them preferred? > Or are they just hardwired to the same thing by chance I believe the other register would work, but I don't have a fused hw to test. OTOH, this is what is commercialized. Btw, the CX_MISC register is not present in all A8x GPUs, for eg: Pakala. -Akhil. > > Konrad