From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx2.zhaoxin.com (mx2.zhaoxin.com [61.152.208.219]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5BBA351C0D for ; Thu, 12 Mar 2026 02:15:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=61.152.208.219 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773281703; cv=none; b=sRGl5J7afSbVEHNQEqEnV9u6osl7u+FRhUZ5M8asbHn2FLQbAZ5mxglbjTr9R7R7rhXJ8mtwJUon+A1LEt1Tw+GoS4HleGEVIGDtzMPXwn432bpmnfJ8fxMxlcvpcSw7n+PMTDAqQVAB8/EgywUIiAPjCiMQrr36YnLJZpU9kkw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773281703; c=relaxed/simple; bh=hWLE1foGDhPuL7SACKce2uJT/0S+Y+y3LVG4rH5Fd5w=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=ZM1OXXN3VNS1gVyUnT0DVyGzjZeUx8+ni8jslJse5ztHS9lQeh6KwxcHQwnUAN99gNz8exEJ3T5RR30SL+brI3lUuScKi7ikg7T68WAuNfhoFCBrZDngSAtjmnI+myO/C/gzHQnxauk3JF97hLOQcO86CL6+o8LgnfHfczCDjjQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com; spf=pass smtp.mailfrom=zhaoxin.com; arc=none smtp.client-ip=61.152.208.219 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zhaoxin.com X-ASG-Debug-ID: 1773281697-1eb14e06ea0c400001-xx1T2L Received: from zhaoxin.com (zxmail.zhaoxin.com [10.28.208.166]) by mx2.zhaoxin.com with ESMTP id FSQrvMgZXvjVPtK5; Thu, 12 Mar 2026 10:14:57 +0800 (CST) X-Barracuda-Envelope-From: TonyWWang-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.208.166 Received: from [10.32.64.22] ([10.32.64.22] [10.32.64.22]) by zhaoxin.com (f222c4) with ESMTPc3cedf1044455b563afe98fbe008502c Thu, 12 Mar 2026 10:14:52 +0800 X-Eyou-Smtpauth: tonywwangoc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.32.64.22 X-Eyou-EnvelopeSender: TonyWWang-oc@zhaoxin.com Message-ID: Date: Thu, 12 Mar 2026 10:14:27 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] x86/cpu/centaur: Disable X86_FEATURE_FSGSBASE on Zhaoxin C4600 To: Dave Hansen , me@ziyao.cc X-ASG-Orig-Subj: Re: [PATCH] x86/cpu/centaur: Disable X86_FEATURE_FSGSBASE on Zhaoxin C4600 Cc: andrew.cooper3@citrix.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, linux-kernel@vger.kernel.org, mingo@redhat.com, stable@vger.kernel.org, tglx@kernel.org, x86@kernel.org, lukelin@viacpu.com, "TimGuo@zhaoxin.com" , cooperyan@zhaoxin.com, benjaminpan@viatech.com, QiyuanWang@zhaoxin.com, HerryYang@zhaoxin.com, "CobeChen@zhaoxin.com" References: <20260228173704.62460-1-me@ziyao.cc> <70139192-54e5-4a4b-bc96-1fe3ec4f7a0b@zhaoxin.com> <7d312ba6-58a0-48cb-92fa-d8094ddef21f@intel.com> Content-Language: en-US From: Tony W Wang-oc In-Reply-To: <7d312ba6-58a0-48cb-92fa-d8094ddef21f@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Eyou-Sender: X-Vid: 59a046b3c32c34b50b4d5a27a426929600@zhaoxin.com X-Barracuda-Connect: zxmail.zhaoxin.com[10.28.208.166] X-Barracuda-Start-Time: 1773281697 X-Barracuda-URL: https://10.28.252.36:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 5106 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=1000.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.155726 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- Hi Dave/Andrew/David/Yaozi, Sorry for the late reply. First of all, this bug was present in certain early ucode patches for ZX-C/ZX-C+ series CPUs; however, it has since been resolved in subsequent updates to the ZX-C/ZX-C+ ucode patch. According to available documentation, the VIA Eden platform supports FSGSBASE; however, this CPU is too old, and we haven't been able to locate actual hardware to test whether it was affected by this bug. It is recommended that, in addition to the existing FMS-based detection, a supplementary check be implemented to identify the specific ucode patch revisions associated with ZX-C/ZX-C+ that are known to exhibit this bug. Due to differences in ucode matching rules on Zhaoxin platforms, existing kernel function interfaces cannot be used, so the patch code has been placed in a vendor-specific file. The specific patching approach can be as follows: --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -8,6 +8,7 @@ #include #include #include +#include #include "cpu.h" @@ -110,6 +111,8 @@ static void early_init_centaur(struct cpuinfo_x86 *c) static void init_centaur(struct cpuinfo_x86 *c) { + u32 chip_pf, dummy; + #ifdef CONFIG_X86_32 char *name; u32 fcr_set = 0; @@ -201,6 +204,18 @@ static void init_centaur(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); #endif + if (c->x86 == 6 && c->x86_model == 15 && c->x86_stepping >= 14) { + native_rdmsr(0x1232, dummy, chip_pf); + chip_pf = (chip_pf >> 15) & 0x7; + c->microcode = intel_get_microcode_revision(); + + if ((chip_pf == 0 && c->microcode < 0x20e) || + (chip_pf == 1 && c->microcode < 0x208)) { + pr_warn_once("CPU has broken FSGSBASE support; clear FSGSBASE feature\n"); + setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); + } + } + init_ia32_feat_ctl(c); } diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c index 031379b7d4fa..0a0525320502 100644 --- a/arch/x86/kernel/cpu/zhaoxin.c +++ b/arch/x86/kernel/cpu/zhaoxin.c @@ -5,6 +5,7 @@ #include #include #include +#include #include "cpu.h" @@ -68,6 +69,8 @@ static void early_init_zhaoxin(struct cpuinfo_x86 *c) static void init_zhaoxin(struct cpuinfo_x86 *c) { + u32 chip_pf, dummy; + early_init_zhaoxin(c); init_intel_cacheinfo(c); @@ -89,6 +92,18 @@ static void init_zhaoxin(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); #endif + if (c->x86 == 6 && c->x86_model == 25 && c->x86_stepping <= 3) { + native_rdmsr(0x1232, dummy, chip_pf); + chip_pf = (chip_pf >> 15) & 0x7; + c->microcode = intel_get_microcode_revision(); + + if ((chip_pf == 0 && c->microcode < 0x20e) || + (chip_pf == 1 && c->microcode < 0x208)) { + pr_warn_once("CPU has broken FSGSBASE support; clear FSGSBASE feature\n"); + setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); + } + } + init_ia32_feat_ctl(c); } Sincerely! TonyWWang-oc On 2026/3/6 00:20, Dave Hansen wrote: > > > [这封邮件来自外部发件人 谨防风险] > > On 3/5/26 01:03, Tony W Wang-oc wrote: >> --- a/arch/x86/kernel/cpu/zhaoxin.c >> +++ b/arch/x86/kernel/cpu/zhaoxin.c >> @@ -89,6 +89,11 @@ static void init_zhaoxin(struct cpuinfo_x86 *c) >> set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); >> #endif >> >> + if (c->x86 == 6 && c->x86_model == 25 && c->x86_stepping <= 3) { >> + pr_warn_once("CPU has broken FSGSBASE support; clear >> FSGSBASE feature\n"); >> + setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); >> + } >> + > > Folks, we have vendor-generic infrastructure to handle these today. You > don't need to hack copied and pasted code across vendor-specific files. > You just need some "VFM" defines for the models: > > #define Z_MODEL_HERE VFM_MAKE(X86_VENDOR_ZHAOXIN, 6, 26) > #define C_MODEL_HERE VFM_MAKE(X86_VENDOR_ZHAOXIN, ...) > > a table: > > static const struct x86_cpu_id bum_fsgsbase[] __initconst = { > X86_MATCH_VFM_STEPS(Z_MODEL_HERE, X86_STEP_MIN, 0x3, 1), > X86_MATCH_VFM_STEPS(C_MODEL_HERE, ..., 1), > }; > > and this code: > > if (x86_match_cpu(bum_fsgsbase)) > setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); > > That code happens _once_. You can even call it from vendor-independent code. > > If you get fixed microcode that can also be extended to store a fixed > microcode version (although we're moving away from doing this on Intel). > > Just please give the models some semi-sane model name.