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Hermes SMTP Server) with ESMTPA ID b726fbcd986fe7e966ab16a9c91a2ad7; Fri, 09 Oct 2026 04:58:13 +0000 (UTC) Message-ID: Date: Fri, 9 Oct 2026 06:58:09 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH net-next v2 5/8] net: dsa: realtek: rtl8365mb: set and get vlan 4k for family D From: Mieczyslaw Nalewaj To: linusw@kernel.org, alsi@bang-olufsen.dk, andrew@lunn.ch, olteanv@gmail.com, kuba@kernel.org, davem@davemloft.net, edumazet@google.com, pabeni@redhat.com, linux@armlinux.org.uk, luizluca@gmail.com, maxime.chevallier@bootlin.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org References: <28382f3f-03c1-4606-9b11-86f118abeafe@yahoo.com> Content-Language: pl In-Reply-To: <28382f3f-03c1-4606-9b11-86f118abeafe@yahoo.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Mailer: WebService/1.1.26668 mail.backend.jedi.jws.acl:role.jedi.acl.token.atz.jws.hermes.yahoo The hardware structure of 4K VLAN table entries has changed between silicon families. Family D's CVLAN entry is two 16-bit words rather than three: there is no third word extending member/untag past bit 7, and no priority/meter fields at all. The FID field is restricted to a narrower 2-bit width. The chip itself supports both IVL and SVL, but this driver always requests IVL for VLAN 4K entries (rtl8365mb_vlan_4k_port_set() sets ivl_en = true on both families), so that control bit is forced here to match existing driver behavior, not a hardware limitation. Reusing the three-word family C layout unconditionally means the third word is read from and written back to the register that holds it on family C, but does not exist as a distinct table word on family D's die; whatever data happens to be there gets folded into member/untag bits [10:8] on read, and re-written on every read-modify-write cycle in rtl8365mb_vlan_4k_port_set(). Give family D its own two-word pack/unpack instead. The two-word layout matches the vendor switch API for this chip family, which writes only 0x0510/0x0511 for a CVLAN entry. Signed-off-by: Mieczyslaw Nalewaj --- drivers/net/dsa/realtek/rtl8365mb_vlan.c | 143 +++++++++++++++-------- 1 file changed, 94 insertions(+), 49 deletions(-) diff --git a/drivers/net/dsa/realtek/rtl8365mb_vlan.c b/drivers/net/dsa/realtek/rtl8365mb_vlan.c index 7add1fb..0466e8c 100644 --- a/drivers/net/dsa/realtek/rtl8365mb_vlan.c +++ b/drivers/net/dsa/realtek/rtl8365mb_vlan.c @@ -55,6 +55,7 @@ /* CVLAN (i.e. VLAN4k) table entry layout, u16[3] */ #define RTL8365MB_CVLAN_ENTRY_SIZE 3 /* 48-bits */ +#define RTL8365MB_D_CVLAN_ENTRY_SIZE 2 /* 32-bits, no 3rd word */ #define RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK GENMASK(7, 0) #define RTL8365MB_CVLAN_MBR_LO_MASK GENMASK(7, 0) #define RTL8365MB_CVLAN_ENTRY_D0_UNTAG_MASK GENMASK(15, 8) @@ -66,6 +67,10 @@ #define RTL8365MB_CVLAN_ENTRY_D1_METERIDX_MASK GENMASK(13, 9) #define RTL8365MB_CVLAN_METERIDX_LO_MASK GENMASK(4, 0) #define RTL8365MB_CVLAN_ENTRY_D1_IVL_SVL_MASK GENMASK(14, 14) +#define RTL8365MB_D_CVLAN_ENTRY_D1_SVLAN_CHK_IVL_SVL_MASK \ + GENMASK(2, 2) +#define RTL8365MB_D_CVLAN_ENTRY_D1_IVL_EN_MASK GENMASK(3, 3) +#define RTL8365MB_D_CVLAN_ENTRY_D1_FID_MASK GENMASK(1, 0) /* extends RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK */ #define RTL8365MB_CVLAN_ENTRY_D2_MBR_EXT_MASK GENMASK(2, 0) #define RTL8365MB_CVLAN_MBR_HI_MASK GENMASK(10, 8) @@ -191,13 +196,16 @@ struct rtl8365mb_vlanmc { static int rtl8365mb_vlan_4k_read(struct realtek_priv *priv, u16 vid, struct rtl8365mb_vlan4k *vlan4k) { + bool is_d = rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D; + size_t entry_size = is_d ? RTL8365MB_D_CVLAN_ENTRY_SIZE : + RTL8365MB_CVLAN_ENTRY_SIZE; u16 data[RTL8365MB_CVLAN_ENTRY_SIZE]; int val; int ret; ret = rtl8365mb_table_query(priv, RTL8365MB_TABLE_CVLAN, RTL8365MB_TABLE_OP_READ, &vid, 0, 0, - data, ARRAY_SIZE(data)); + data, entry_size); if (ret) return ret; @@ -205,33 +213,51 @@ static int rtl8365mb_vlan_4k_read(struct realtek_priv *priv, u16 vid, memset(vlan4k, 0, sizeof(*vlan4k)); vlan4k->vid = vid; + /* member/untag: d0[7:0]/d0[15:8] on both families. Family C + * extends these into data[2] bits [2:0]/[5:3] for its 9th-11th + * ports; family D's die has only 8 ports and no third table + * word, so data[2] does not exist there and must not be read. + */ val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK, data[0]); vlan4k->member = FIELD_PREP(RTL8365MB_CVLAN_MBR_LO_MASK, val); - val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_MBR_EXT_MASK, data[2]); - vlan4k->member |= FIELD_PREP(RTL8365MB_CVLAN_MBR_HI_MASK, val); + if (!is_d) { + val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_MBR_EXT_MASK, data[2]); + vlan4k->member |= FIELD_PREP(RTL8365MB_CVLAN_MBR_HI_MASK, val); + } val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D0_UNTAG_MASK, data[0]); vlan4k->untag = FIELD_PREP(RTL8365MB_CVLAN_UNTAG_LO_MASK, val); - val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_UNTAG_EXT_MASK, data[2]); - vlan4k->untag |= FIELD_PREP(RTL8365MB_CVLAN_UNTAG_HI_MASK, val); - - vlan4k->fid = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_FID_MASK, data[1]); - vlan4k->priority_en = - FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_VBPEN_MASK, data[1]); - vlan4k->priority = - FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_VBPRI_MASK, data[1]); - vlan4k->policing_en = - FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_ENVLANPOL_MASK, data[1]); - - val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_METERIDX_MASK, data[1]); - val = FIELD_PREP(RTL8365MB_CVLAN_METERIDX_LO_MASK, val); - vlan4k->meteridx = val; - val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_METERIDX_EXT_MASK, data[2]); - val = FIELD_PREP(RTL8365MB_CVLAN_METERIDX_HI_MASK, val); - vlan4k->meteridx |= val; - - vlan4k->ivl_en = - FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_IVL_SVL_MASK, data[1]); + if (!is_d) { + val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_UNTAG_EXT_MASK, data[2]); + vlan4k->untag |= FIELD_PREP(RTL8365MB_CVLAN_UNTAG_HI_MASK, val); + } + + if (is_d) { + vlan4k->fid = FIELD_GET(RTL8365MB_D_CVLAN_ENTRY_D1_FID_MASK, data[1]); + /* Family D has no priority/meter fields in this entry - + * left zeroed by the memset() above. + */ + vlan4k->ivl_en = + FIELD_GET(RTL8365MB_D_CVLAN_ENTRY_D1_IVL_EN_MASK, data[1]); + } else { + vlan4k->fid = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_FID_MASK, data[1]); + vlan4k->priority_en = + FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_VBPEN_MASK, data[1]); + vlan4k->priority = + FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_VBPRI_MASK, data[1]); + vlan4k->policing_en = + FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_ENVLANPOL_MASK, data[1]); + + val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_METERIDX_MASK, data[1]); + val = FIELD_PREP(RTL8365MB_CVLAN_METERIDX_LO_MASK, val); + vlan4k->meteridx = val; + val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_METERIDX_EXT_MASK, data[2]); + val = FIELD_PREP(RTL8365MB_CVLAN_METERIDX_HI_MASK, val); + vlan4k->meteridx |= val; + + vlan4k->ivl_en = + FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_IVL_SVL_MASK, data[1]); + } return 0; } @@ -239,6 +265,9 @@ static int rtl8365mb_vlan_4k_read(struct realtek_priv *priv, u16 vid, static int rtl8365mb_vlan_4k_write(struct realtek_priv *priv, const struct rtl8365mb_vlan4k *vlan4k) { + bool is_d = rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D; + size_t entry_size = is_d ? RTL8365MB_D_CVLAN_ENTRY_SIZE : + RTL8365MB_CVLAN_ENTRY_SIZE; u16 data[RTL8365MB_CVLAN_ENTRY_SIZE] = { 0 }; u16 vid; int val; @@ -250,36 +279,52 @@ static int rtl8365mb_vlan_4k_write(struct realtek_priv *priv, val = FIELD_GET(RTL8365MB_CVLAN_UNTAG_LO_MASK, vlan4k->untag); data[0] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D0_UNTAG_MASK, val); - data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_FID_MASK, vlan4k->fid); - data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_VBPEN_MASK, - vlan4k->priority_en); - data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_VBPRI_MASK, - vlan4k->priority); - data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_ENVLANPOL_MASK, - vlan4k->policing_en); - - /* FIELD_* does not play nice with struct bitfield. */ - val = vlan4k->meteridx; - val = FIELD_GET(RTL8365MB_CVLAN_METERIDX_LO_MASK, val); - data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_METERIDX_MASK, val); - - data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_IVL_SVL_MASK, - vlan4k->ivl_en); - - val = FIELD_GET(RTL8365MB_CVLAN_MBR_HI_MASK, vlan4k->member); - data[2] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D2_MBR_EXT_MASK, val); - - val = FIELD_GET(RTL8365MB_CVLAN_UNTAG_HI_MASK, vlan4k->untag); - data[2] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D2_UNTAG_EXT_MASK, val); - - val = vlan4k->meteridx; - val = FIELD_GET(RTL8365MB_CVLAN_METERIDX_HI_MASK, val); - data[2] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D2_METERIDX_EXT_MASK, val); + if (is_d) { + /* The chip supports both IVL and SVL, but the caller (see + * rtl8365mb_vlan_4k_port_set()) never requests SVL, so both + * IVL/SVL selector bits are forced here rather than threaded + * through from vlan4k->ivl_en, which family C does honor. + */ + data[1] |= FIELD_PREP(RTL8365MB_D_CVLAN_ENTRY_D1_IVL_EN_MASK, 1) | + FIELD_PREP(RTL8365MB_D_CVLAN_ENTRY_D1_SVLAN_CHK_IVL_SVL_MASK, 1); + data[1] |= FIELD_PREP(RTL8365MB_D_CVLAN_ENTRY_D1_FID_MASK, vlan4k->fid); + /* No priority/meter/member-untag-extension fields exist in + * family D's 2-word entry - data[1] and data[0] above are + * the whole entry, and data[2] is not part of it at all. + */ + } else { + val = vlan4k->fid; + data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_FID_MASK, val); + data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_VBPEN_MASK, + vlan4k->priority_en); + data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_VBPRI_MASK, + vlan4k->priority); + data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_ENVLANPOL_MASK, + vlan4k->policing_en); + + /* FIELD_* does not play nice with struct bitfield. */ + val = vlan4k->meteridx; + val = FIELD_GET(RTL8365MB_CVLAN_METERIDX_LO_MASK, val); + data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_METERIDX_MASK, val); + + data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_IVL_SVL_MASK, + vlan4k->ivl_en); + + val = FIELD_GET(RTL8365MB_CVLAN_MBR_HI_MASK, vlan4k->member); + data[2] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D2_MBR_EXT_MASK, val); + + val = FIELD_GET(RTL8365MB_CVLAN_UNTAG_HI_MASK, vlan4k->untag); + data[2] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D2_UNTAG_EXT_MASK, val); + + val = vlan4k->meteridx; + val = FIELD_GET(RTL8365MB_CVLAN_METERIDX_HI_MASK, val); + data[2] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D2_METERIDX_EXT_MASK, val); + } vid = vlan4k->vid; return rtl8365mb_table_query(priv, RTL8365MB_TABLE_CVLAN, RTL8365MB_TABLE_OP_WRITE, &vid, 0, 0, - data, ARRAY_SIZE(data)); + data, entry_size); } static int -- 2.53.0