From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751321AbdAaQTM (ORCPT ); Tue, 31 Jan 2017 11:19:12 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:44266 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751108AbdAaQTC (ORCPT ); Tue, 31 Jan 2017 11:19:02 -0500 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E30DA60314 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=cov@codeaurora.org Subject: Re: [PATCH v5 2/2] arm64: Work around Falkor erratum 1009 To: Will Deacon References: <20170130230818.9848-1-cov@codeaurora.org> <20170130230818.9848-2-cov@codeaurora.org> <20170131143843.GD22283@arm.com> Cc: Jonathan Corbet , Marc Zyngier , Catalin Marinas , linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mark Rutland , linux-kernel@vger.kernel.org, shankerd@codeaurora.org, timur@codeaurora.org, Mark Langsdorf , Mark Salter , Jon Masters , Neil Leeder From: Christopher Covington Message-ID: Date: Tue, 31 Jan 2017 11:17:03 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2 MIME-Version: 1.0 In-Reply-To: <20170131143843.GD22283@arm.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/31/2017 09:38 AM, Will Deacon wrote: > On Mon, Jan 30, 2017 at 06:08:17PM -0500, Christopher Covington wrote: >> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h >> index deab52374119..fc434f421c7b 100644 >> --- a/arch/arm64/include/asm/tlbflush.h >> +++ b/arch/arm64/include/asm/tlbflush.h >> @@ -36,9 +36,21 @@ >> * not. The macros handles invoking the asm with or without the >> * register argument as appropriate. >> */ >> -#define __TLBI_0(op, arg) asm ("tlbi " #op) >> -#define __TLBI_1(op, arg) asm ("tlbi " #op ", %0" : : "r" (arg)) >> -#define __TLBI_N(op, arg, n, ...) __TLBI_##n(op, arg) >> +#define __TLBI_0(op, arg) asm volatile ("tlbi " #op "\n" \ >> + ALTERNATIVE("nop\n nop", \ >> + "dsb ish\n tlbi " #op, \ >> + ARM64_WORKAROUND_REPEAT_TLBI, \ >> + CONFIG_QCOM_FALKOR_ERRATUM_1009) \ >> + : : ) >> + >> +#define __TLBI_1(op, arg) asm volatile ("tlbi " #op ", %0\n" \ >> + ALTERNATIVE("nop\n nop", \ >> + "dsb ish\n tlbi " #op ", %0", \ >> + ARM64_WORKAROUND_REPEAT_TLBI, \ >> + CONFIG_QCOM_FALKOR_ERRATUM_1009) \ >> + : : "r" (arg)) >> + > > Why are these now volatile? I asked the same question on the previous > version but didn't get a response: > > http://lists.infradead.org/pipermail/linux-arm-kernel/2017-January/483579.html D'oh! Will fix in v6. Sorry about that. Cov -- Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.