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From: Michal Simek <michal.simek@amd.com>
To: Krzysztof Kozlowski <krzk@kernel.org>,
	Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Cc: git@amd.com
Subject: Re: [PATCH] dt-bindings: soc: Add new board description for Versal NET
Date: Wed, 8 Jan 2025 16:27:28 +0100	[thread overview]
Message-ID: <b198c395-5aa1-418a-82fb-936377c3caa2@amd.com> (raw)
In-Reply-To: <8ff20f2c-fe72-48a6-ad00-872ca20f5e8c@kernel.org>



On 1/8/25 12:47, Krzysztof Kozlowski wrote:
> On 08/01/2025 12:33, Shubhrajyoti Datta wrote:
>>   description: |
>> -  Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
>> +  Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC or Versal Adaptive SoCs
>>   
>>   properties:
>>     $nodename:
>> @@ -187,6 +187,10 @@ properties:
>>             - const: qemu,mbv
>>             - const: amd,mbv
>>   
>> +      - description: Xilinx Versal NET
>> +        items:
>> +          - const: xlnx,versal-net
> 
> It is usually too difficult to use SoCs on their own. Just too small
> pins for our clumsy fingers. Therefore I don't get how this is supposed
> to be used...
> 
> Anyway, provide the user for the binding (DTS).

ok. Let us strip our current DT from descriptions which are not upstreamed yet 
and wire one board to be also listed.

Thanks,
Michal

  reply	other threads:[~2025-01-08 15:27 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-08 11:33 Shubhrajyoti Datta
2025-01-08 11:47 ` Krzysztof Kozlowski
2025-01-08 15:27   ` Michal Simek [this message]
2025-01-10 16:00 ` Rob Herring
2025-01-21  7:51   ` Michal Simek
2025-01-22 16:03   ` Michal Simek

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