From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D9EA922A4E1 for ; Tue, 9 Dec 2025 14:49:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765291749; cv=none; b=HjWYFb8mfhmE0MHjWuEx0b8zFUkzLq7HHvzuNHkoqVpYCPxTZE4Zxy52C6KeMR/y7SFmmUqr4sgP6OVF0YzLtOl0W4Qx0W9gMNz6UttscldljkhlfI1fjGY5SzeAKZ0WXfRea42Jp29KeP9CFBjeYVpGIOWVBHcbS+A8tAX5NC0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765291749; c=relaxed/simple; bh=2E+Ugf4BdD4nzqXG3EPyb0O7iV/V15ApkeGEBp3Zf7Q=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=VceuMVYB0xmHXh476Wk0odBAOARVMH/TF8xS1KTp9bkZK/eK8teJuHbNx8wenSv1rdu6fnCFGhrOGi1AYOghWFK1iZbmxiLuYpbzEmDpxmbqKbYgQWDI8cIwisld6kWy59sQovsvSsepn5jqrW7wUDc09q2mHplzpxKZE0kmo1Y= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AB73B175D; Tue, 9 Dec 2025 06:48:58 -0800 (PST) Received: from [10.1.196.46] (e134344.arm.com [10.1.196.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A2B163F73B; Tue, 9 Dec 2025 06:49:02 -0800 (PST) Message-ID: Date: Tue, 9 Dec 2025 14:49:01 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 01/38] arm64: mpam: Context switch the MPAM registers To: James Morse , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal References: <20251205215901.17772-1-james.morse@arm.com> <20251205215901.17772-2-james.morse@arm.com> From: Ben Horgan Content-Language: en-US In-Reply-To: <20251205215901.17772-2-james.morse@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi James, On 12/5/25 21:58, James Morse wrote: > MPAM allows traffic in the SoC to be labeled by the OS, these labels > are used to apply policy in caches and bandwidth regulators, and to > monitor traffic in the SoC. The label is made up of a PARTID and PMG > value. The x86 equivalent calls these CLOSID and RMID, but they don't > map precisely. > [...] > > All this should depend on whether there is an MPAM driver, hide > it behind CONFIG_MPAM. CONFIG_MPAM -> CONFIG_ARM64_MPAM > > CC: Amit Singh Tomar > Signed-off-by: James Morse > --- > arch/arm64/Kconfig | 2 + > arch/arm64/include/asm/mpam.h | 74 ++++++++++++++++++++++++++++ > arch/arm64/include/asm/thread_info.h | 3 ++ > arch/arm64/kernel/Makefile | 1 + > arch/arm64/kernel/mpam.c | 13 +++++ > arch/arm64/kernel/process.c | 7 +++ > drivers/resctrl/mpam_devices.c | 2 - > drivers/resctrl/mpam_internal.h | 2 + > 8 files changed, 102 insertions(+), 2 deletions(-) > create mode 100644 arch/arm64/include/asm/mpam.h > create mode 100644 arch/arm64/kernel/mpam.c > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 004d58cfbff8..558baa9e7c08 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -2048,6 +2048,8 @@ config ARM64_MPAM > > MPAM is exposed to user-space via the resctrl pseudo filesystem. > > + This option enables the extra context switch code. > + > endmenu # "ARMv8.4 architectural features" > > menu "ARMv8.5 architectural features" > diff --git a/arch/arm64/include/asm/mpam.h b/arch/arm64/include/asm/mpam.h > new file mode 100644 > index 000000000000..86a55176f884 > --- /dev/null > +++ b/arch/arm64/include/asm/mpam.h > @@ -0,0 +1,74 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* Copyright (C) 2025 Arm Ltd. */ > + > +#ifndef __ASM__MPAM_H > +#define __ASM__MPAM_H > + > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +DECLARE_STATIC_KEY_FALSE(mpam_enabled); > +DECLARE_PER_CPU(u64, arm64_mpam_default); > +DECLARE_PER_CPU(u64, arm64_mpam_current); > + > +/* > + * The value of the MPAM0_EL1 sysreg when a task is in resctrl's default group. > + * This is used by the context switch code to use the resctrl CPU property > + * instead. The value is modified when CDP is enabled/disabled by mounting > + * the resctrl filesystem. > + */ > +extern u64 arm64_mpam_global_default; > + > +/* > + * The resctrl filesystem writes to the partid/pmg values for threads and CPUs, > + * which may race with reads in __mpam_sched_in(). Ensure only one of the old > + * or new values are used. Particular care should be taken with the pmg field > + * as __mpam_sched_in() may read a partid and pmg that don't match, causing > + * this value to be stored with cache allocations, despite being considered > + * 'free' by resctrl. __mpam_sched_in() -> mpam_thread_switch() This is called from resctrl_arch_sched_in(). > + * > + * A value in struct thread_info is used instead of struct task_struct as the > + * cpu's u64 register format is used, but struct task_struct has two u32'. > + */ > +static inline u64 mpam_get_regval(struct task_struct *tsk) > +{ > +#ifdef CONFIG_ARM64_MPAM > + return READ_ONCE(task_thread_info(tsk)->mpam_partid_pmg); > +#else > + return 0; > +#endif > +} > + > +static inline void mpam_thread_switch(struct task_struct *tsk) > +{ > + u64 oldregval; > + int cpu = smp_processor_id(); > + u64 regval = mpam_get_regval(tsk); > + > + if (!IS_ENABLED(CONFIG_ARM64_MPAM) || > + !static_branch_likely(&mpam_enabled)) > + return; > + > + if (regval == READ_ONCE(arm64_mpam_global_default)) > + regval = READ_ONCE(per_cpu(arm64_mpam_default, cpu)); > + > + oldregval = READ_ONCE(per_cpu(arm64_mpam_current, cpu)); > + if (oldregval == regval) > + return; > + > + write_sysreg_s(regval, SYS_MPAM1_EL1); > + isb(); > + > + /* Synchronising the EL0 write is left until the ERET to EL0 */ > + write_sysreg_s(regval, SYS_MPAM0_EL1); > + > + WRITE_ONCE(per_cpu(arm64_mpam_current, cpu), regval); > +} > +#endif /* __ASM__MPAM_H */ > diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h > index f241b8601ebd..c226dabd5019 100644 > --- a/arch/arm64/include/asm/thread_info.h > +++ b/arch/arm64/include/asm/thread_info.h > @@ -41,6 +41,9 @@ struct thread_info { > #ifdef CONFIG_SHADOW_CALL_STACK > void *scs_base; > void *scs_sp; > +#endif > +#ifdef CONFIG_ARM64_MPAM > + u64 mpam_partid_pmg; > #end if > u32 cpu; > }; > diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile > index 76f32e424065..15979f366519 100644 > --- a/arch/arm64/kernel/Makefile > +++ b/arch/arm64/kernel/Makefile > @@ -67,6 +67,7 @@ obj-$(CONFIG_CRASH_DUMP) += crash_dump.o > obj-$(CONFIG_VMCORE_INFO) += vmcore_info.o > obj-$(CONFIG_ARM_SDE_INTERFACE) += sdei.o > obj-$(CONFIG_ARM64_PTR_AUTH) += pointer_auth.o > +obj-$(CONFIG_ARM64_MPAM) += mpam.o > obj-$(CONFIG_ARM64_MTE) += mte.o > obj-y += vdso-wrap.o > obj-$(CONFIG_COMPAT_VDSO) += vdso32-wrap.o > diff --git a/arch/arm64/kernel/mpam.c b/arch/arm64/kernel/mpam.c > new file mode 100644 > index 000000000000..9866d2ca0faa > --- /dev/null > +++ b/arch/arm64/kernel/mpam.c > @@ -0,0 +1,13 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* Copyright (C) 2025 Arm Ltd. */ > + > +#include > + > +#include > +#include > + > +DEFINE_STATIC_KEY_FALSE(mpam_enabled); > +DEFINE_PER_CPU(u64, arm64_mpam_default); > +DEFINE_PER_CPU(u64, arm64_mpam_current); > + > +u64 arm64_mpam_global_default; > diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c > index fba7ca102a8c..b510c0699313 100644 > --- a/arch/arm64/kernel/process.c > +++ b/arch/arm64/kernel/process.c > @@ -51,6 +51,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -737,6 +738,12 @@ struct task_struct *__switch_to(struct task_struct *prev, > if (prev->thread.sctlr_user != next->thread.sctlr_user) > update_sctlr_el1(next->thread.sctlr_user); > > + /* > + * MPAM thread switch happens after the DSB to ensure prev's accesses > + * use prev's MPAM settings. > + */ > + mpam_thread_switch(next); > + > /* the actual thread switch */ > last = cpu_switch_to(prev, next); > > diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c > index 0b5b158e1aaf..2996ad93fc3e 100644 > --- a/drivers/resctrl/mpam_devices.c > +++ b/drivers/resctrl/mpam_devices.c > @@ -29,8 +29,6 @@ > > #include "mpam_internal.h" > > -DEFINE_STATIC_KEY_FALSE(mpam_enabled); /* This moves to arch code */ > - > /* > * mpam_list_lock protects the SRCU lists when writing. Once the > * mpam_enabled key is enabled these lists are read-only, > diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_internal.h > index e79c3c47259c..4508a6654fe0 100644 > --- a/drivers/resctrl/mpam_internal.h > +++ b/drivers/resctrl/mpam_internal.h > @@ -17,6 +17,8 @@ > #include > #include > > +#include > + > #define MPAM_MSC_MAX_NUM_RIS 16 > > struct platform_device; The DECLARE_STATIC_KEY_FALSE(mpam_enabled) on the next line can now be removed. Thanks, Ben