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Wed, 30 Oct 2024 17:52:17 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49UHqGi1015906 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Oct 2024 17:52:16 GMT Received: from [10.216.35.255] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 30 Oct 2024 10:52:11 -0700 Message-ID: Date: Wed, 30 Oct 2024 23:22:08 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 02/11] clk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLs To: Christophe JAILLET , Bjorn Andersson , Michael Turquette , "Stephen Boyd" , Abhishek Sahu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , "Stephen Boyd" , , , , , References: <20241019-qcs615-mm-clockcontroller-v1-0-4cfb96d779ae@quicinc.com> <20241019-qcs615-mm-clockcontroller-v1-2-4cfb96d779ae@quicinc.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 2NVBuc5c9uwG282KIp6GcXxW4_gTJ8KA X-Proofpoint-ORIG-GUID: 2NVBuc5c9uwG282KIp6GcXxW4_gTJ8KA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 impostorscore=0 mlxscore=0 suspectscore=0 adultscore=0 clxscore=1011 phishscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410300140 On 10/19/2024 1:50 AM, Christophe JAILLET wrote: >> + >> +static int clk_alpha_pll_slew_update(struct clk_alpha_pll *pll) >> +{ >> +    int ret = 0; > > Nitpick: unneeded initialisation > Will fix in the next patch. >> +    u32 val; >> + >> +    regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, >> PLL_UPDATE); >> +    regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); >> + >> +    ret = wait_for_pll_update(pll); >> +    if (ret) >> +        return ret; >> +    /* >> +     * Hardware programming mandates a wait of at least 570ns before >> polling the LOCK >> +     * detect bit. Have a delay of 1us just to be safe. >> +     */ >> +    mb(); >> +    udelay(1); >> + >> +    return wait_for_pll_enable_lock(pll); >> +} > > ... > >> +static int clk_alpha_pll_slew_enable(struct clk_hw *hw) >> +{ >> +    int rc; >> + >> +    rc = clk_alpha_pll_calibrate(hw); >> +    if (rc) >> +        return rc; >> + >> +    rc = clk_alpha_pll_enable(hw); >> + >> +    return rc; > > Nitpick: return clk_alpha_pll_enable(hw); Will fix in the next patch. -- Thanks & Regards, Taniya Das.