Re: [PATCH v2 8/8] irqchip, gicv3-its, cma: Use CMA for allocation of large device tables

[Shanker Donthineni <shankerd@codeaurora.org>]

Hi Marc/Robert,

On 03/16/2017 08:41 AM, Marc Zyngier wrote:
> On 16/03/17 13:31, Robert Richter wrote:
>> On 15.03.17 18:46:22, Marc Zyngier wrote:
>>> On 15/03/17 18:37, Robert Richter wrote:
>>>> On 14.03.17 12:40:45, Shanker Donthineni wrote:
>>>>>> @@ -1698,6 +1706,9 @@ static int __init its_init_one(struct its_node *its)
>>>>>>  		return err;
>>>>>>  	}
>>>>>>  
>>>>>> +	/* Setup dma_ops for dmam_alloc_coherent() */
>>>>>> +	arch_setup_dma_ops(&its->dev, 0, 0, NULL, true);
>>>>>> +
>>>>> Why you are hard-coding DMA coherent property to true here ? It
>>>>> breaks the MSI(x) functionally on systems where ITS hardware doesn't
>>>>> support coherency.
>>>> Aren't current ITS tables coherent only?
>>> No, there is no such guarantee. Actually, there is strictly no need for
>>> coherency, as the ITS tables are only written by the ITS itself, for its
>>> own purpose.
>> So no need to change that, right?
> I don't think there is any. We just need to allocate memory with the
> relevant constraints (alignment and zeroing, mostly), and make sure we
> never access it directly. Of course, property tables and command queues
> would benefit from being allocated as DMA buffers, which would allow the
> cache flush to be dealt with at the DMA level.

Agree with Marc, only PROP tables and CMD queue buffers are touched by CPU during runtime. That means DMA coherent property set to true only when both the CMD_BASE (ITS_FLAGS_CMDQ_NEEDS_FLUSHING) and PROP_BASE (RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) tables support coherency.

> Thanks,
>
> 	M.

-- 
Shanker Donthineni
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.