From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.4 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D0DEC433DB for ; Tue, 2 Feb 2021 16:15:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1893D64F55 for ; Tue, 2 Feb 2021 16:15:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235081AbhBBQPx (ORCPT ); Tue, 2 Feb 2021 11:15:53 -0500 Received: from mx.socionext.com ([202.248.49.38]:24641 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236073AbhBBQOA (ORCPT ); Tue, 2 Feb 2021 11:14:00 -0500 Received: from unknown (HELO iyokan2-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 03 Feb 2021 01:13:17 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan2-ex.css.socionext.com (Postfix) with ESMTP id A61A32059027; Wed, 3 Feb 2021 01:13:17 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Wed, 3 Feb 2021 01:13:17 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan2.css.socionext.com (Postfix) with ESMTP id 00C77B1D40; Wed, 3 Feb 2021 01:13:17 +0900 (JST) Received: from [10.212.20.246] (unknown [10.212.20.246]) by yuzu.css.socionext.com (Postfix) with ESMTP id 511FE120148; Wed, 3 Feb 2021 01:13:16 +0900 (JST) Subject: Re: [PATCH v2 3/3] PCI: uniphier-ep: Add EPC restart management support To: Kishon Vijay Abraham I , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar References: <1611500977-24816-1-git-send-email-hayashi.kunihiko@socionext.com> <1611500977-24816-4-git-send-email-hayashi.kunihiko@socionext.com> From: Kunihiko Hayashi Message-ID: Date: Wed, 3 Feb 2021 01:13:15 +0900 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Kishon, Thank you for your comment. On 2021/01/28 23:29, Kishon Vijay Abraham I wrote: > Hi Kunihiko, > > On 24/01/21 8:39 pm, Kunihiko Hayashi wrote: >> Set the polling function and call the init function to enable EPC restart >> management. The polling function detects that the bus-reset signal is a >> rising edge. >> >> Signed-off-by: Kunihiko Hayashi >> --- >> drivers/pci/controller/dwc/Kconfig | 1 + >> drivers/pci/controller/dwc/pcie-uniphier-ep.c | 44 ++++++++++++++++++++++++++- >> 2 files changed, 44 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig >> index 22c5529..90d400a 100644 >> --- a/drivers/pci/controller/dwc/Kconfig >> +++ b/drivers/pci/controller/dwc/Kconfig >> @@ -302,6 +302,7 @@ config PCIE_UNIPHIER_EP >> depends on OF && HAS_IOMEM >> depends on PCI_ENDPOINT >> select PCIE_DW_EP >> + select PCI_ENDPOINT_RESTART >> help >> Say Y here if you want PCIe endpoint controller support on >> UniPhier SoCs. This driver supports Pro5 SoC. >> diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c >> index 69810c6..9d83850 100644 >> --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c >> +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c >> @@ -26,6 +26,7 @@ >> #define PCL_RSTCTRL_PIPE3 BIT(0) >> >> #define PCL_RSTCTRL1 0x0020 >> +#define PCL_RSTCTRL_PERST_MON BIT(16) >> #define PCL_RSTCTRL_PERST BIT(0) >> >> #define PCL_RSTCTRL2 0x0024 >> @@ -60,6 +61,7 @@ struct uniphier_pcie_ep_priv { >> struct clk *clk, *clk_gio; >> struct reset_control *rst, *rst_gio; >> struct phy *phy; >> + bool bus_reset_status; >> const struct pci_epc_features *features; >> }; >> >> @@ -212,6 +214,41 @@ uniphier_pcie_get_features(struct dw_pcie_ep *ep) >> return priv->features; >> } >> >> +static bool uniphier_pcie_ep_poll_reset(void *data) >> +{ >> + struct uniphier_pcie_ep_priv *priv = data; >> + bool ret, status; >> + >> + if (!priv) >> + return false; >> + >> + status = !(readl(priv->base + PCL_RSTCTRL1) & PCL_RSTCTRL_PERST_MON); >> + >> + /* return true if the rising edge of bus reset is detected */ >> + ret = !!(status == false && priv->bus_reset_status == true); >> + priv->bus_reset_status = status; > > I'm still not convinced about having a separate library for restart > management but shouldn't we reset the function driver on falling edge? I understand your opnion well. There might not be enough way to give controller-specific features to handle "restart" as a common function. > After the rising edge the host expects the endpoint to be ready. I see. I didn't consider that restart was completed just after the rising edge. > Why not use the CORE_INIT (core_init_notifier) infrastructure? I don't follow the CORE_INIT yet, so I'll try to introduce it into the driver. However, our current controller doesn't have an interrupt that detects PERST like pcie-tegra194. I think the driver needs a thread for polling PERST like patch 2/3. Thank you, --- Best Regards Kunihiko Hayashi