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Wed, 05 Nov 2025 03:47:21 -0800 (PST) X-Google-Smtp-Source: AGHT+IF5ab+BuIMW7EEe8KGrCPBR+KCmyAPB1gT2l4Arx0WUviGh0Gta1z8ZmjeET1gPTGcz1MSzNg== X-Received: by 2002:a17:90b:4b86:b0:32e:a8b7:e9c with SMTP id 98e67ed59e1d1-341a6de90aamr3359432a91.29.1762343240996; Wed, 05 Nov 2025 03:47:20 -0800 (PST) Received: from [10.217.217.147] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-341a68ce9e9sm2635595a91.9.2025.11.05.03.47.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 05 Nov 2025 03:47:20 -0800 (PST) Message-ID: Date: Wed, 5 Nov 2025 17:17:14 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC] arm64: dts: qcom: x1e80100: Fix USB combo PHYs SS1 and SS2 ref clocks To: Abel Vesa , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak , Sibi Sankar Cc: Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251103-dts-qcom-x1e80100-fix-combo-ref-clks-v1-1-f395ec3cb7e8@linaro.org> Content-Language: en-US From: Taniya Das In-Reply-To: <20251103-dts-qcom-x1e80100-fix-combo-ref-clks-v1-1-f395ec3cb7e8@linaro.org> Content-Type: text/plain; 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These gates are part of the TCSR clock controller. > > At least on Dell XPS 13 (9345), if the ref clock provided by the TCSR > clock controller for SS1 PHY is disabled on the clk_disable_unused late > initcall, the PHY fails to initialize. It doesn't happen on the SS0 PHY > and the SS2 is not used on this device. > > This doesn't seem to be a problem on CRD though. It might be that the > RPMh has a vote for it from some other consumer and does not actually > disable it when ther kernel drops its vote. > > Either way, these TCSR provided clocks seem to be the correct ones for > the SS1 and SS2, so use them instead. > > Fixes: 4af46b7bd66f ("arm64: dts: qcom: x1e80100: Add USB nodes") > Signed-off-by: Abel Vesa > --- > I dropped the clk_ignore_unused on my XPS13 a while ago, but only > realized now that usb_1_ss1_qmpphy (the left hand Type-C port) > doesn't initialize successfully. > > Traced it to the TCSR_USB_4_2_CLKREF_EN and then checked the Glymur DT > patchset. It seems it already does this for the SS1 and SS2 PHYs: > https://lore.kernel.org/all/20250925-v3_glymur_introduction-v1-23-24b601bbecc0@oss.qualcomm.com/ > > I think replacing the bi_tcxo is the better option, since the bi_tcxo > is already the parent of every clock provided by the TCSR, including > these for the SS1 and SS2 combo PHYs. > --- > arch/arm64/boot/dts/qcom/hamoa.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi > index a17900eacb20396a9792efcfcd6ce6dd877435d1..9c9e567731556ff532fa64c7595e2570b0597da3 100644 > --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi > +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi > @@ -2937,7 +2937,7 @@ usb_1_ss1_qmpphy: phy@fda000 { > reg = <0 0x00fda000 0 0x4000>; > > clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, > - <&rpmhcc RPMH_CXO_CLK>, > + <&tcsr TCSR_USB4_1_CLKREF_EN>, > <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, > <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; > clock-names = "aux", > @@ -3008,7 +3008,7 @@ usb_1_ss2_qmpphy: phy@fdf000 { > reg = <0 0x00fdf000 0 0x4000>; > > clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, > - <&rpmhcc RPMH_CXO_CLK>, > + <&tcsr TCSR_USB4_2_CLKREF_EN>, > <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, > <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; > clock-names = "aux", > > --- Reviewed-by: Taniya Das -- Thanks, Taniya Das