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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id w25-20020a2e9599000000b002b34735dc72sm1300665ljh.108.2023.06.16.04.36.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 Jun 2023 04:36:25 -0700 (PDT) Message-ID: Date: Fri, 16 Jun 2023 13:36:23 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Content-Language: en-US To: Mohammad Rafi Shaik , krzysztof.kozlowski+dt@linaro.org, swboyd@chromium.org, andersson@kernel.org, broonie@kernel.org, agross@kernel.org Cc: robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_rohkumar@quicinc.com, srinivas.kandagatla@linaro.org, dianders@chromium.org, judyhsiao@chromium.org, quic_visr@quicinc.com, Srinivasa Rao Mandadapu References: <20230616103534.4031331-1-quic_mohs@quicinc.com> <20230616103534.4031331-9-quic_mohs@quicinc.com> From: Konrad Dybcio Subject: Re: [RESEND v6 8/8] arm64: dts: qcom: sc7280: Add qcom,adsp-pil-mode property in clock nodes In-Reply-To: <20230616103534.4031331-9-quic_mohs@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 16.06.2023 12:35, Mohammad Rafi Shaik wrote: > From: Srinivasa Rao Mandadapu > > Add "qcom,adsp-pil-mode" property in clock nodes for herobrine > crd revision 3 board specific device tree. > This is to register clocks conditionally by differentiating ADSP > based platforms and legacy path platforms. > Also disable lpass_core clock, as it is creating conflict > with ADSP clocks and it is not required for ADSP based platforms. > > Signed-off-by: Srinivasa Rao Mandadapu > Signed-off-by: Mohammad Rafi Shaik > --- > .../qcom/sc7280-herobrine-audioreach-wcd9385.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi > index c02ca393378f..876a29178d46 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi > @@ -197,6 +197,14 @@ q6prmcc: clock-controller { > }; > }; > > +&lpass_aon { > + qcom,adsp-pil-mode; That's a whole bunch of hacky bindings that makes no sense.. What should have been done from the beginning is: - all clocks should be registered inside the clock driver, unconditionally as far as .c code is concerned - the regmap properties within should reflect the actual max register range within the hardware block - device-tree should contain protected-clocks, which omits registering specified clks (I guess in the ADSP-less case you could probably even register all of them and it wouldn't hurt) > +}; > + > +&lpass_core { > + status = "disabled"; status = "reserved"; Konrad > +}; > + > &lpass_rx_macro { > /delete-property/ power-domains; > /delete-property/ power-domain-names; > @@ -239,3 +247,7 @@ &lpass_va_macro { > > status = "okay"; > }; > + > +&lpasscc { > + qcom,adsp-pil-mode; > +};