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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82379c53f6bsm17123370b3a.63.2026.02.01.20.38.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 01 Feb 2026 20:38:42 -0800 (PST) Message-ID: Date: Mon, 2 Feb 2026 10:08:35 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 3/4] arm64: dts: qcom: Introduce Glymur base dtsi To: Abel Vesa Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jyothi Kumar Seerapu , Maulik Shah , Sibi Sankar , Taniya Das , Kamal Wadhwa , Qiang Yu , Manaf Meethalavalappu Pallikunhi , Jishnu Prakash , Abel Vesa References: <20260122-upstream_v3_glymur_introduction-v6-0-245f408ed82a@oss.qualcomm.com> <20260122-upstream_v3_glymur_introduction-v6-3-245f408ed82a@oss.qualcomm.com> <2vqho236mjlsnraqif6ivic6ybblnsmk4litqw2sbfpjvrp2t2@eztnjrlsmrp6> <64x5xfzjik4qtvsxqvwqhf5mua3rpvh7nzw67v5sy7afoo5fzv@5vp3uvjk66if> Content-Language: en-US From: Pankaj Patil In-Reply-To: <64x5xfzjik4qtvsxqvwqhf5mua3rpvh7nzw67v5sy7afoo5fzv@5vp3uvjk66if> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: fudgtnbopM04LyhezwvscY6Tp2W97VBt X-Proofpoint-ORIG-GUID: fudgtnbopM04LyhezwvscY6Tp2W97VBt X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjAyMDAzNyBTYWx0ZWRfX0nGJV+1csX6E JJNquo8ZOArHOtE88LyvQpe3yAqciGDrOfGPlbMgcC2Ag1QVaMqP03xvE2BwzqsQn4RTzAsckG6 qpCwdZ+A9YY8zapmGCy1F7chSUKbMHPdlLhZpYAL0rQnxv+2ASSYiUWjVdlgqRtNTZH7OHyYdeq 4clebfF8NoC8bsfi7wXA0ePO7yvG5npdpIbAYZftY9iK+5af6INiIX6PHF95DRh5YJQLvo9xtES zBgVJTES+YgEwxWFYZG5bwmW7LycKF629qEDHvYnt/sbn0nDAsGcVtAN9wvnImG6olPEcGMJPVS CkWcK3/cYp/vM+iPaePZLtvkTwl9oRy9//3gWQWT7hco+7jvzizIdzJElWVKXSaz0+lYoVJcnfy 2JuXrAi3TELTpMU+2DUqm57IDTAiOpVHofMozjHkJFZp4iRNpsmtB5ZGyikSg+SjbdOpyIMQgga AoPkpu3PSGM0qQGTJDA== X-Authority-Analysis: v=2.4 cv=T8OBjvKQ c=1 sm=1 tr=0 ts=69802a54 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=Hoo0Bpfwwk8gRiAXly0A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-02_01,2026-01-30_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 clxscore=1015 suspectscore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602020037 On 1/31/2026 3:30 AM, Abel Vesa wrote: > On 26-01-30 23:44:43, Abel Vesa wrote: >> On 26-01-22 20:54:00, Pankaj Patil wrote: >>> Introduce the base device tree support for Glymur – Qualcomm's >>> next-generation compute SoC. The new glymur.dtsi describes the core SoC >>> components, including: >>> >>> - CPUs and CPU topology >>> - Interrupt controller and TLMM >>> - GCC,DISPCC and RPMHCC clock controllers >>> - Reserved memory and interconnects >>> - APPS and PCIe SMMU and firmware SCM >>> - Watchdog, RPMHPD, APPS RSC and SRAM >>> - PSCI and PMU nodes >>> - QUPv3 serial engines >>> - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS >>> - PDP0 mailbox, IPCC and AOSS >>> - Display clock controller >>> - SPMI PMIC arbiter with SPMI0/1/2 buses >>> - SMP2P nodes >>> - TSENS and thermal zones (8 instances, 92 sensors) >>> >>> Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104, >>> PMH0110, PMIC's along with temp-alarm and GPIO nodes needed on Glymur >>> >>> Enabled PCIe controllers and associated PHY to support boot to >>> shell with nvme storage, >>> List of PCIe instances enabled: >>> >>> - PCIe3b >>> - PCIe4 >>> - PCIe5 >>> - PCIe6 >>> >>> Co-developed-by: Jyothi Kumar Seerapu >>> Signed-off-by: Jyothi Kumar Seerapu >>> Co-developed-by: Maulik Shah >>> Signed-off-by: Maulik Shah >>> Co-developed-by: Sibi Sankar >>> Signed-off-by: Sibi Sankar >>> Co-developed-by: Taniya Das >>> Signed-off-by: Taniya Das >>> Co-developed-by: Kamal Wadhwa >>> Signed-off-by: Kamal Wadhwa >>> Co-developed-by: Qiang Yu >>> Signed-off-by: Qiang Yu >>> Co-developed-by: Abel Vesa >>> Signed-off-by: Abel Vesa >>> Co-developed-by: Manaf Meethalavalappu Pallikunhi >>> Signed-off-by: Manaf Meethalavalappu Pallikunhi >>> Co-developed-by: Jishnu Prakash >>> Signed-off-by: Jishnu Prakash >>> Signed-off-by: Pankaj Patil >>> --- >>> arch/arm64/boot/dts/qcom/glymur.dtsi | 5913 ++++++++++++++++++++++++++ >>> arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 187 + >>> arch/arm64/boot/dts/qcom/pmh0101.dtsi | 68 + >>> arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 144 + >>> arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi | 144 + >>> arch/arm64/boot/dts/qcom/pmk8850.dtsi | 70 + >>> arch/arm64/boot/dts/qcom/smb2370.dtsi | 45 + >>> 7 files changed, 6571 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi >>> new file mode 100644 >>> index 000000000000..16a3c3ecf97a >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi >> >> [...] >> >>> + >>> + soc: soc@0 { >>> + compatible = "simple-bus"; >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; >>> + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; >>> + >>> + gcc: clock-controller@100000 { >>> + compatible = "qcom,glymur-gcc"; >>> + reg = <0x0 0x00100000 0x0 0x1f9000>; >>> + clocks = <&rpmhcc RPMH_CXO_CLK>, >>> + <&rpmhcc RPMH_CXO_CLK_A>, >>> + <&sleep_clk>, >>> + <0>, >>> + <0>, >>> + <0>, >>> + <0>, >>> + <0>, >>> + <0>, >>> + <0>, >>> + <0>, >>> + <0>, >>> + <0>, >>> + <0>, >>> + <0>, >>> + <0>, >>> + <0>, >>> + <0>, >>> + <0>, >>> + <0>, >>> + <&pcie3b_phy>, >>> + <&pcie4_phy>, >>> + <&pcie5_phy>, >>> + <&pcie6_phy>, >> >> I'm afraid these do not match the array from the driver. >> I think there is one more <0> before the pcie3b. > > Actually, one less. > >> >> Please double check. 1 clock was removed in v4 to fix the no of clocks, 44 was incorrect I will update it to match the array from the driver >> >> Thanks, >> Abel