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([2600:8803:e7e4:500:90d7:b13f:c53:8ca3]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-68448c1c15dsm3873975eaf.0.2026.04.06.08.02.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Apr 2026 08:02:30 -0700 (PDT) Message-ID: Date: Mon, 6 Apr 2026 10:02:29 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 4/4] iio: adc: ad4691: add SPI offload support To: "Sabau, Radu bogdan" , Lars-Peter Clausen , "Hennerich, Michael" , Jonathan Cameron , "Sa, Nuno" , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski , Philipp Zabel , Jonathan Corbet , Shuah Khan Cc: "linux-iio@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pwm@vger.kernel.org" , "linux-gpio@vger.kernel.org" , "linux-doc@vger.kernel.org" References: <20260403-ad4692-multichannel-sar-adc-driver-v6-0-fa2a01a57c4e@analog.com> <20260403-ad4692-multichannel-sar-adc-driver-v6-4-fa2a01a57c4e@analog.com> <1d0d41c8-7867-4459-a91a-a2c6774b1885@baylibre.com> <420dba4a-0c31-47bc-b84a-5d29702b115e@baylibre.com> Content-Language: en-US From: David Lechner In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 4/6/26 9:16 AM, Sabau, Radu bogdan wrote: > > >> -----Original Message----- >> From: David Lechner >> Sent: Monday, April 6, 2026 4:44 PM > > ... > >>> >>> This is bad documentation on my part. "channel byte" isn't used anymore, >>> this is previous version behaviour. Right now, only 16-bits worth of actual >>> channel data are used. >>> >> Then why do we need the shift if there is no other data? Can't we rework >> the SPI message so that there is no shift? > > I thought the shift is needed since DMA size is 32 bits, and value comes on the > upper word 16 bits, not on the lower ones as for CNV Burst. That should only happen if we are reading 32-bits instead of 16 bits. We should be able to set up the SPI xfers so that we only read 16 bits. > > Manual Mode layout: TX [CMD_HI CMD_LO DUMMY DUMMY], RX [DATA_HI DATA_LO DUMMY DUMMY] > CNV Burst layout: TX [REG_HI REG_LO DUMMY DUMMY], RX [DUMMY DUMMY DATA_HI DATA_LO] This can be split in two xfers. CNV Burst layout: TX [REG_HI REG_LO] RX [DATA_HI DATA_LO] And we could even set bits_per_word to 16 so that the data is CPU endian instead of big endian when doing SPI offloading.