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Sun, 22 Feb 2026 22:18:18 -0800 From: Nicolin Chen To: CC: , , , , , , , , , , , Subject: [PATCH v12 2/8] iommu/arm-smmu-v3: Explicitly set smmu_domain->stage for SVA Date: Sun, 22 Feb 2026 22:18:03 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A672E:EE_|DS0PR12MB8069:EE_ X-MS-Office365-Filtering-Correlation-Id: 6427ba22-2abe-4009-4cce-08de72a36392 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?K0d/HCz766y3ESg81IYpS3AdwFtvYbvUSKGxyC2S+DhCkjLUbM0Lb6HjLLNw?= =?us-ascii?Q?bJ3yZL3QLlTBmNYAhv91NKVBdxOal6qUNvGSj2EVzWgpdRVzA/lshdGQL/rO?= =?us-ascii?Q?9n1FA0DGFpMa+Nfg7Y0a95sVF11jDi2yt2Q1qhxBnnQWmK8UUyqqMSKZWLXE?= =?us-ascii?Q?td5Md1wYJ9OyVlapL5j6PcjxvcrBcCuGCaBu9KK6CuurQJghQmvx4fmIHsl+?= =?us-ascii?Q?wyuh+XuVVu2rxbJ98/ZRuhIsmoiN+kfgCJk70taAweLrDU8YL3paaUQE0Pmf?= =?us-ascii?Q?s1U89hzrLuW4Zgka+ko6g35Mc85BZr7TLQmt2TEyCxCkY36go3SPxmq4ewo5?= =?us-ascii?Q?P+TjE6dAEDz3CfKwg0HKA/4LYCo3Jn2c/SAPEQv1UKfUDiff0d8s4W3GYaGm?= =?us-ascii?Q?siU09gW/Peqm1//t/ELAKC/CUZbVsJykuD4wWLf3/5WkJmXNaye4FU5Foxvh?= =?us-ascii?Q?JW70rsD1lVoXeWi3IKt0njHNW1vT/AgBCkABlLf8tfGGPhIdoHfY0fclDCaY?= =?us-ascii?Q?0e3+kY6AtiZmww5jlVmSlDWKakMMMC3JCGtwbwLsDp1wHCoo0lu95T8Ak9Gy?= =?us-ascii?Q?0UTkaizgSryHigC6OC4BKY3VFUty5SQxkfBfYLaotG4vkhh1q4o4DSGjn/Hs?= =?us-ascii?Q?4TIA6DGOzLf6TIT5wGI2K37FXxJrIvoXNwQzctIY7ZH2vcLhrueRFz7gNb/g?= =?us-ascii?Q?tyvHu4+aYUMjENiSNEJZ0g23C8Yvkza1SHVbXE7x0XxVMNC9HQ4YJkZ8H0eG?= =?us-ascii?Q?cSdgh7iegb2zwkASneOmjAqJLq2PUqeOG/QA30iSaM46hUs7+Ox/iSbgXeH5?= =?us-ascii?Q?fLKDQATfRMFvcsVUdOf4IpX6IRZDzwCyXjrs4VVAKpTYv89gqbKEUDls7IPf?= =?us-ascii?Q?Fhz3Fr4UsbSQH+s4Og9iN/OJ/BDRucxKy0bVw0PWJjUtdgFV9QPXLcVsNDJo?= =?us-ascii?Q?DL4hlMW1s+hI79wYPOWBUoRc0sh0s5ajih0uvzud83iy8OiOTQIGmLrgvbpr?= =?us-ascii?Q?j3C5jzAEC71mX5ZDi6+FncTbLqb8K17LktpfHRlAVQXTm2hOj9RbfZqbN9nN?= =?us-ascii?Q?IzpyxPEfnj2rCU+/B7DaVFi4yx2MAM+bhe4so19anyU5wdrzofY8SMfkF9nk?= =?us-ascii?Q?TSRGAfv50ZD5UbkLborzYRwKKUYkggxdAINeRhKrgnRmqi3uN47grRxSw5LS?= =?us-ascii?Q?xX7tJFqJPy+XEDiDx0USGWiWHBs+9xZMB/uVGGm4up2abr4tShBc/gRLFV0q?= =?us-ascii?Q?BVf2Md75wCQyIQsehTXbBpSixVOvBCQwYC7hh9ore37R4uLeqvCVZhaV1m8P?= =?us-ascii?Q?vFb43pQp9zgESMky4cOurAaHtA8B+4o9xdXgraW3NIHVgfHTDoMUwx5gKS12?= =?us-ascii?Q?XyyHLwEg2U5vcRMRXPKJ9P4T7hSm+6bfowU79OZb04WCvHn5BBFHPxq6Wasv?= =?us-ascii?Q?yFOQ/q+OJ1TFnqjcus2megXG6jNrf08BbAEBho2QZ8yEyDMQgwVslmToB951?= =?us-ascii?Q?wXWDXJuFAdXLEhHpvlxz9CNXlLdur2n45jaUn/TZ+zG60S7y1/76yUGI/Fdb?= =?us-ascii?Q?5nqLDo6rHWX2+E54xkuQB7i+nnOiatQetZqqbip60h5CqKMwqy/GjOr6hOea?= =?us-ascii?Q?lWyVC2/z5h0F+sUl8VhiRWm0rxH4PV3gKtQRnx1YnvIiiZs4PrsFVu40sKQ/?= =?us-ascii?Q?VRkJmA=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: tdtFX1NscTqs1rT3Iudp2/1qyTuC3CLmhGjcymIi5EOidlsZFXr1IQ7ulm9SHpEQACHF0GmSbqhPv48IYD4NmSvx6gSdyTOTEF0KMIOmlGFykIep2V3A8AGGrobeqvxgKMt69A5GBXYHFkW6sj/oV1Dm7AVoIinCsGyakvTeHM3Q0V2kAZuNPHgDpzEFbRRiFeQGwnfwdSMzoWxODaAFmkSDuxMZ79ayxVvUp9K61DJluBWrK0wWC4yn697FJSuz9UDgkwzFYxQkMhuWFXBN8HD/nF6AisEG4JgHYiT9mFGytWX5KDgDq3CF2jBjhu+EniwUIbe1cDAjyYSVPVaG9iD1C8Ymct1xBw5QYlit1Y3CtX18Hflc1Q1SjoR5qt+C7pgIsQLqojYuPlwLbVdCjp29k9nIUJsmpcKFsykaWroF/Vk4psypHh6216XX4fJo X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2026 06:18:40.7511 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6427ba22-2abe-4009-4cce-08de72a36392 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A672E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8069 Both the ARM_SMMU_DOMAIN_S1 case and the SVA case use ASID, requiring ASID based invalidation commands to flush the TLB. Define an ARM_SMMU_DOMAIN_SVA to make the SVA case clear to share the same path with the ARM_SMMU_DOMAIN_S1 case, which will be a part of the routine to build a new per-domain invalidation array. There is no function change. Suggested-by: Jason Gunthorpe Acked-by: Balbir Singh Reviewed-by: Jason Gunthorpe Reviewed-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +++ 3 files changed, 5 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 3c6d65d36164f..24894b1630045 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -856,6 +856,7 @@ struct arm_smmu_master { enum arm_smmu_domain_stage { ARM_SMMU_DOMAIN_S1 = 0, ARM_SMMU_DOMAIN_S2, + ARM_SMMU_DOMAIN_SVA, }; struct arm_smmu_domain { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 59a480974d80f..6097f1f540d87 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -346,6 +346,7 @@ struct iommu_domain *arm_smmu_sva_domain_alloc(struct device *dev, * ARM_SMMU_FEAT_RANGE_INV is present */ smmu_domain->domain.pgsize_bitmap = PAGE_SIZE; + smmu_domain->stage = ARM_SMMU_DOMAIN_SVA; smmu_domain->smmu = smmu; ret = xa_alloc(&arm_smmu_asid_xa, &asid, smmu_domain, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 606abe051e68b..117979c96b762 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3132,6 +3132,9 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev, arm_smmu_install_ste_for_dev(master, &target); arm_smmu_clear_cd(master, IOMMU_NO_PASID); break; + default: + WARN_ON(true); + break; } arm_smmu_attach_commit(&state); -- 2.43.0