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Mon, 28 Apr 2025 08:10:02 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 53S8A2lT005357 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Apr 2025 08:10:02 GMT Received: from [10.239.133.49] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 28 Apr 2025 01:09:58 -0700 Message-ID: Date: Mon, 28 Apr 2025 16:09:56 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/2] dt-bindings: arm: Add Qualcomm extended CTI To: Krzysztof Kozlowski , Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , References: <20240903121847.6964-1-quic_jinlmao@quicinc.com> <20240903121847.6964-2-quic_jinlmao@quicinc.com> <8d203417-e3da-4969-87ea-f77cdb720756@kernel.org> <04d46109-d499-4e91-88aa-4187145b811d@quicinc.com> Content-Language: en-US From: Jinlong Mao In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI4MDA2NiBTYWx0ZWRfX9eHyGZaWihej jfrUeqzbopu3ZaXzKip2Xx6PCy0Kt84KlXPp3AhQKqJewb9HkpbyqT8W8L2RbnP35rBcJy4jTiR 9Z0UMitfi6fjm+A7E4qoj1KLxT4kSPR0FY16MRs4PAAdFF+wLt6QYPAxb1VmljAi+xSW96ogPCc BtZOjD4v+zKib0vtdplC2aRmh4XtA51VnVQEgfH3iSBS1RSu+syQ/GqBtwLnq1uebjK7Yjti6L/ jakkRZ+4IADmGF1GrjwS/ivQd/YDVNhsNzJP7Grf1iCu6S1bG+VXJXcbkk7cg2R+3i8PP84PkxE FXi/NcpQzGZo1ya1y6CkH8T0fGbp5F5zPOWrrqOtrBes+Z52bnc/fgNNEcB3awXdcJt4NJhOR7b ha35vtMUz0gHLd/f9DrfPAJE+zcWFZx/5NfkwsOCXQPvdE1j+opFF1vHmlmDJn960INkDJVE X-Proofpoint-GUID: dL9IIffQcO9w4mMrV81tiS6lhBQH1eiZ X-Proofpoint-ORIG-GUID: dL9IIffQcO9w4mMrV81tiS6lhBQH1eiZ X-Authority-Analysis: v=2.4 cv=C8fpyRP+ c=1 sm=1 tr=0 ts=680f37da cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=BB5YKCej9nSSSTOgEYYA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-28_03,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 spamscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504280066 On 2025/4/28 15:39, Krzysztof Kozlowski wrote: > On 28/04/2025 09:31, Jinlong Mao wrote: >> >> >> On 2024/9/3 20:42, Krzysztof Kozlowski wrote: >>> On 03/09/2024 14:18, Mao Jinlong wrote: >>>> Add Qualcomm extended CTI support in CTI binding file. Qualcomm >>>> extended CTI supports up to 128 triggers. >>>> >>>> Signed-off-by: Mao Jinlong >>>> --- >>>> .../devicetree/bindings/arm/arm,coresight-cti.yaml | 14 ++++++++++++++ >>>> 1 file changed, 14 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >>>> index 6a73eaa66a42..141efba7c697 100644 >>>> --- a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >>>> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >>>> @@ -87,6 +87,10 @@ properties: >>>> - const: arm,coresight-cti-v8-arch >>>> - const: arm,coresight-cti >>>> - const: arm,primecell >>>> + - items: >>>> + - const: qcom,coresight-cti-extended >>> >>> That's just enum in previous entry/list. >> Sorry for the late response. This is a new CTI type. Need the three >> items in compatible at the same time, just like other kind of CTIs. > > > Comment stays valid, you did not address it at all. Hi Krzysztof, Do you mean we only need const: qcom,coresight-cti-extended here ? No need const: arm,coresight-cti and const: arm,primecell as they are in previous entry/list, right ? > >> >>> >>>> + - const: arm,coresight-cti >>>> + - const: arm,primecell >>>> >>>> reg: >>>> maxItems: 1 >>>> @@ -254,6 +258,16 @@ examples: >>>> clocks = <&soc_smc50mhz>; >>>> clock-names = "apb_pclk"; >>>> }; >>>> + # minimum extended CTI definition. >>>> + - | >>> >>> No need for new example. No differences here. >> This is a new type CTI. > > > Comment stays valid, you did not address it at all. > > Best regards, > Krzysztof