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([2001:818:ea56:d000:94c4:fb0e:28f:2a8d]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48323c0296dsm163879985e9.1.2026.02.08.01.15.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Feb 2026 01:15:02 -0800 (PST) Message-ID: Subject: Re: [PATCH v2 3/4] dt-bindings: iio: adc: ad4080: add AD4880 support From: Nuno =?ISO-8859-1?Q?S=E1?= To: Krzysztof Kozlowski , Antoniu Miclaus Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?ISO-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Date: Sun, 08 Feb 2026 09:16:06 +0000 In-Reply-To: <20260207-evasive-mastodon-of-apotheosis-e663a1@quoll> References: <290f35bcbd2f1ee68333ff65f89b54ec7fbb9c53.1770393792.git.antoniu.miclaus@analog.com> <20260207-evasive-mastodon-of-apotheosis-e663a1@quoll> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2 (3.56.2-2.fc42) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Sat, 2026-02-07 at 11:41 +0100, Krzysztof Kozlowski wrote: > On Fri, Feb 06, 2026 at 06:07:15PM +0200, Antoniu Miclaus wrote: > > Add support for the AD4880, a dual-channel 20-bit 40MSPS SAR ADC > > with integrated fully differential amplifiers (FDA). > >=20 > > The AD4880 has two independent ADC channels, each with its own SPI > > configuration interface. This requires: > > - Two entries in reg property for primary and secondary channel chip se= lects >=20 > Please wrap commit message according to Linux coding style / submission > process (neither too early nor over the limit): > https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/su= bmitting-patches.rst#L597 >=20 > Please run scripts/checkpatch.pl on the patches and fix reported > warnings. >=20 > > - Two io-backends entries for the two data channels > >=20 > > Signed-off-by: Antoniu Miclaus > > --- > > Changes in v2: > > =C2=A0 - Replace custom adi,aux-spi-cs property with standard reg prope= rty > > =C2=A0=C2=A0=C2=A0 containing two entries for multi-channel devices > > =C2=A0 - Add conditional schema validation for reg and io-backends base= d on > > =C2=A0=C2=A0=C2=A0 compatible string > > =C2=A0 - Update example to use reg =3D <0 1> instead of adi,aux-spi-cs > > =C2=A0 - Add AD4880 datasheet link > >=20 > > =C2=A0.../bindings/iio/adc/adi,ad4080.yaml=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 | 51 ++++++++++++++++++- > > =C2=A01 file changed, 49 insertions(+), 2 deletions(-) > >=20 > > diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml > > b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml > > index ccd6a0ac1539..7108a91bb0bf 100644 > > --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml > > +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml > > @@ -18,7 +18,11 @@ description: | > > =C2=A0=C2=A0 service a wide variety of precision, wide bandwidth data a= cquisition > > =C2=A0=C2=A0 applications. > > =C2=A0 > > +=C2=A0 The AD4880 is a dual-channel variant with two independent ADC c= hannels, > > +=C2=A0 each with its own SPI configuration interface. > > + > > =C2=A0=C2=A0 https://www.analog.com/media/en/technical-documentation/da= ta-sheets/ad4080.pdf > > +=C2=A0 https://www.analog.com/media/en/technical-documentation/data-sh= eets/ad4880.pdf > > =C2=A0 > > =C2=A0$ref: /schemas/spi/spi-peripheral-props.yaml# > > =C2=A0 > > @@ -31,9 +35,15 @@ properties: > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - adi,ad4084 > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - adi,ad4086 > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - adi,ad4087 > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - adi,ad4880 > > =C2=A0 > > =C2=A0=C2=A0 reg: > > -=C2=A0=C2=A0=C2=A0 maxItems: 1 > > +=C2=A0=C2=A0=C2=A0 minItems: 1 > > +=C2=A0=C2=A0=C2=A0 maxItems: 2 > > +=C2=A0=C2=A0=C2=A0 description: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 SPI chip select(s). For single-channel = devices, one chip select. > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 For multi-channel devices like AD4880, = two chip selects are required > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 as each channel has its own SPI configu= ration interface. > > =C2=A0 > > =C2=A0=C2=A0 spi-max-frequency: > > =C2=A0=C2=A0=C2=A0=C2=A0 description: Configuration of the SPI bus. > > @@ -57,7 +67,8 @@ properties: > > =C2=A0=C2=A0 vrefin-supply: true > > =C2=A0 > > =C2=A0=C2=A0 io-backends: > > -=C2=A0=C2=A0=C2=A0 maxItems: 1 > > +=C2=A0=C2=A0=C2=A0 minItems: 1 > > +=C2=A0=C2=A0=C2=A0 maxItems: 2 >=20 > Instead list the items with minItems, so the order is defined. >=20 Also looks like we now need 'io-backend-names'. - Nuno S=C3=A1 > >=20