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[84.160.116.233]) by smtp.gmail.com with ESMTPSA id z21-20020a1709063a1500b006da6436819dsm12313957eje.173.2022.04.11.13.49.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 13:49:51 -0700 (PDT) Date: Mon, 11 Apr 2022 22:49:49 +0200 From: Philipp Hortmann To: Forest Bond , Greg Kroah-Hartman , linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 6/7] staging: vt6655: Replace VNSvOutPortD with iowrite32 Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Replace macro VNSvOutPortD with iowrite32. The name of macro and the arguments use CamelCase which is not accepted by checkpatch.pl For constants from 0 to below 0x80000000 the u32 cast was omitted. For variables which are defined as unsigned long the u32 is omitted. Since there are more than one checkpatch issue per line, more steps are rquired to fix. Signed-off-by: Philipp Hortmann --- V1 -> V2: Patch was not existing V2 -> V3: Inserted patch that was before in a different way in "Rename macros VNSvOutPortB,W,D" This patch was part of 5/6 and is now 6/7 --- drivers/staging/vt6655/baseband.c | 2 +- drivers/staging/vt6655/card.c | 27 +++++++++---------- drivers/staging/vt6655/device_main.c | 14 ++++------ drivers/staging/vt6655/mac.h | 39 ++++++++++++++-------------- drivers/staging/vt6655/rf.c | 2 +- drivers/staging/vt6655/upc.h | 3 --- 6 files changed, 38 insertions(+), 49 deletions(-) diff --git a/drivers/staging/vt6655/baseband.c b/drivers/staging/vt6655/baseband.c index 4f1c44127e03..3b3211d0077a 100644 --- a/drivers/staging/vt6655/baseband.c +++ b/drivers/staging/vt6655/baseband.c @@ -2014,7 +2014,7 @@ bool bb_vt3253_init(struct vnt_private *priv) byVT3253B0_AGC4_RFMD2959[ii][0], byVT3253B0_AGC4_RFMD2959[ii][1]); - VNSvOutPortD(iobase + MAC_REG_ITRTMSET, 0x23); + iowrite32(0x23, iobase + MAC_REG_ITRTMSET); MACvRegBitsOn(iobase, MAC_REG_PAPEDELAY, BIT(0)); } priv->abyBBVGA[0] = 0x18; diff --git a/drivers/staging/vt6655/card.c b/drivers/staging/vt6655/card.c index 57b9ea385690..8701a3a6b46f 100644 --- a/drivers/staging/vt6655/card.c +++ b/drivers/staging/vt6655/card.c @@ -294,10 +294,8 @@ bool CARDbUpdateTSF(struct vnt_private *priv, unsigned char byRxRate, qwTSFOffset = CARDqGetTSFOffset(byRxRate, qwBSSTimestamp, local_tsf); /* adjust TSF, HW's TSF add TSF Offset reg */ - VNSvOutPortD(priv->port_offset + MAC_REG_TSFOFST, - (u32)qwTSFOffset); - VNSvOutPortD(priv->port_offset + MAC_REG_TSFOFST + 4, - (u32)(qwTSFOffset >> 32)); + iowrite32((u32)qwTSFOffset, priv->port_offset + MAC_REG_TSFOFST); + iowrite32((u32)(qwTSFOffset >> 32), priv->port_offset + MAC_REG_TSFOFST + 4); MACvRegBitsOn(priv->port_offset, MAC_REG_TFTCTL, TFTCTL_TSFSYNCEN); } @@ -330,9 +328,8 @@ bool CARDbSetBeaconPeriod(struct vnt_private *priv, iowrite16(wBeaconInterval, priv->port_offset + MAC_REG_BI); priv->wBeaconInterval = wBeaconInterval; /* Set NextTBTT */ - VNSvOutPortD(priv->port_offset + MAC_REG_NEXTTBTT, (u32)qwNextTBTT); - VNSvOutPortD(priv->port_offset + MAC_REG_NEXTTBTT + 4, - (u32)(qwNextTBTT >> 32)); + iowrite32((u32)qwNextTBTT, priv->port_offset + MAC_REG_NEXTTBTT); + iowrite32((u32)(qwNextTBTT >> 32), priv->port_offset + MAC_REG_NEXTTBTT + 4); MACvRegBitsOn(priv->port_offset, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN); return true; @@ -554,7 +551,7 @@ void CARDvSetRSPINF(struct vnt_private *priv, u8 bb_type) /* swap over to get correct write order */ swap(phy.swap[0], phy.swap[1]); - VNSvOutPortD(priv->port_offset + MAC_REG_RSPINF_B_1, phy.field_write); + iowrite32(phy.field_write, priv->port_offset + MAC_REG_RSPINF_B_1); /* RSPINF_b_2 */ vnt_get_phy_field(priv, 14, @@ -563,7 +560,7 @@ void CARDvSetRSPINF(struct vnt_private *priv, u8 bb_type) swap(phy.swap[0], phy.swap[1]); - VNSvOutPortD(priv->port_offset + MAC_REG_RSPINF_B_2, phy.field_write); + iowrite32(phy.field_write, priv->port_offset + MAC_REG_RSPINF_B_2); /* RSPINF_b_5 */ vnt_get_phy_field(priv, 14, @@ -572,7 +569,7 @@ void CARDvSetRSPINF(struct vnt_private *priv, u8 bb_type) swap(phy.swap[0], phy.swap[1]); - VNSvOutPortD(priv->port_offset + MAC_REG_RSPINF_B_5, phy.field_write); + iowrite32(phy.field_write, priv->port_offset + MAC_REG_RSPINF_B_5); /* RSPINF_b_11 */ vnt_get_phy_field(priv, 14, @@ -581,7 +578,7 @@ void CARDvSetRSPINF(struct vnt_private *priv, u8 bb_type) swap(phy.swap[0], phy.swap[1]); - VNSvOutPortD(priv->port_offset + MAC_REG_RSPINF_B_11, phy.field_write); + iowrite32(phy.field_write, priv->port_offset + MAC_REG_RSPINF_B_11); /* RSPINF_a_6 */ s_vCalculateOFDMRParameter(RATE_6M, @@ -800,8 +797,8 @@ void CARDvSetFirstNextTBTT(struct vnt_private *priv, qwNextTBTT = CARDqGetNextTBTT(qwNextTBTT, wBeaconInterval); /* Set NextTBTT */ - VNSvOutPortD(iobase + MAC_REG_NEXTTBTT, (u32)qwNextTBTT); - VNSvOutPortD(iobase + MAC_REG_NEXTTBTT + 4, (u32)(qwNextTBTT >> 32)); + iowrite32((u32)qwNextTBTT, iobase + MAC_REG_NEXTTBTT); + iowrite32((u32)(qwNextTBTT >> 32), iobase + MAC_REG_NEXTTBTT + 4); MACvRegBitsOn(iobase, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN); } @@ -826,8 +823,8 @@ void CARDvUpdateNextTBTT(struct vnt_private *priv, u64 qwTSF, qwTSF = CARDqGetNextTBTT(qwTSF, wBeaconInterval); /* Set NextTBTT */ - VNSvOutPortD(iobase + MAC_REG_NEXTTBTT, (u32)qwTSF); - VNSvOutPortD(iobase + MAC_REG_NEXTTBTT + 4, (u32)(qwTSF >> 32)); + iowrite32((u32)qwTSF, iobase + MAC_REG_NEXTTBTT); + iowrite32((u32)(qwTSF >> 32), iobase + MAC_REG_NEXTTBTT + 4); MACvRegBitsOn(iobase, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN); pr_debug("Card:Update Next TBTT[%8llx]\n", qwTSF); } diff --git a/drivers/staging/vt6655/device_main.c b/drivers/staging/vt6655/device_main.c index bd97e3b9bc98..8de225701ca1 100644 --- a/drivers/staging/vt6655/device_main.c +++ b/drivers/staging/vt6655/device_main.c @@ -1522,20 +1522,16 @@ static void vnt_configure(struct ieee80211_hw *hw, if (priv->mc_list_count > 2) { MACvSelectPage1(priv->port_offset); - VNSvOutPortD(priv->port_offset + - MAC_REG_MAR0, 0xffffffff); - VNSvOutPortD(priv->port_offset + - MAC_REG_MAR0 + 4, 0xffffffff); + iowrite32((u32)0xffffffff, priv->port_offset + MAC_REG_MAR0); + iowrite32((u32)0xffffffff, priv->port_offset + MAC_REG_MAR0 + 4); MACvSelectPage0(priv->port_offset); } else { MACvSelectPage1(priv->port_offset); - VNSvOutPortD(priv->port_offset + - MAC_REG_MAR0, (u32)multicast); - VNSvOutPortD(priv->port_offset + - MAC_REG_MAR0 + 4, - (u32)(multicast >> 32)); + iowrite32((u32)multicast, priv->port_offset + MAC_REG_MAR0); + iowrite32((u32)(multicast >> 32), + priv->port_offset + MAC_REG_MAR0 + 4); MACvSelectPage0(priv->port_offset); } diff --git a/drivers/staging/vt6655/mac.h b/drivers/staging/vt6655/mac.h index 9e8f7e1f1655..4827f370b5ad 100644 --- a/drivers/staging/vt6655/mac.h +++ b/drivers/staging/vt6655/mac.h @@ -568,8 +568,7 @@ do { \ /* set the chip with current BCN tx descriptor address */ #define MACvSetCurrBCNTxDescAddr(iobase, dwCurrDescAddr) \ - VNSvOutPortD(iobase + MAC_REG_BCNDMAPTR, \ - dwCurrDescAddr) + iowrite32((u32)(dwCurrDescAddr), iobase + MAC_REG_BCNDMAPTR) /* set the chip with current BCN length */ #define MACvSetCurrBCNLength(iobase, wCurrBCNLength) \ @@ -603,19 +602,19 @@ do { \ iowrite8(HOSTCR_MACEN | HOSTCR_RXON | HOSTCR_TXON, iobase + MAC_REG_HOSTCR) #define MACvRx0PerPktMode(iobase) \ - VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, RX_PERPKT) + iowrite32(RX_PERPKT, iobase + MAC_REG_RXDMACTL0) #define MACvRx1PerPktMode(iobase) \ - VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, RX_PERPKT) + iowrite32(RX_PERPKT, iobase + MAC_REG_RXDMACTL1) #define MACvReceive0(iobase) \ do { \ unsigned long dwData; \ dwData = ioread32(iobase + MAC_REG_RXDMACTL0); \ if (dwData & DMACTL_RUN) \ - VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, DMACTL_WAKE); \ + iowrite32(DMACTL_WAKE, iobase + MAC_REG_RXDMACTL0); \ else \ - VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, DMACTL_RUN); \ + iowrite32(DMACTL_RUN, iobase + MAC_REG_RXDMACTL0); \ } while (0) #define MACvReceive1(iobase) \ @@ -623,9 +622,9 @@ do { \ unsigned long dwData; \ dwData = ioread32(iobase + MAC_REG_RXDMACTL1); \ if (dwData & DMACTL_RUN) \ - VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, DMACTL_WAKE); \ + iowrite32(DMACTL_WAKE, iobase + MAC_REG_RXDMACTL1); \ else \ - VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, DMACTL_RUN); \ + iowrite32(DMACTL_RUN, iobase + MAC_REG_RXDMACTL1); \ } while (0) #define MACvTransmit0(iobase) \ @@ -633,9 +632,9 @@ do { \ unsigned long dwData; \ dwData = ioread32(iobase + MAC_REG_TXDMACTL0); \ if (dwData & DMACTL_RUN) \ - VNSvOutPortD(iobase + MAC_REG_TXDMACTL0, DMACTL_WAKE); \ + iowrite32(DMACTL_WAKE, iobase + MAC_REG_TXDMACTL0); \ else \ - VNSvOutPortD(iobase + MAC_REG_TXDMACTL0, DMACTL_RUN); \ + iowrite32(DMACTL_RUN, iobase + MAC_REG_TXDMACTL0); \ } while (0) #define MACvTransmitAC0(iobase) \ @@ -643,9 +642,9 @@ do { \ unsigned long dwData; \ dwData = ioread32(iobase + MAC_REG_AC0DMACTL); \ if (dwData & DMACTL_RUN) \ - VNSvOutPortD(iobase + MAC_REG_AC0DMACTL, DMACTL_WAKE); \ + iowrite32(DMACTL_WAKE, iobase + MAC_REG_AC0DMACTL); \ else \ - VNSvOutPortD(iobase + MAC_REG_AC0DMACTL, DMACTL_RUN); \ + iowrite32(DMACTL_RUN, iobase + MAC_REG_AC0DMACTL); \ } while (0) #define MACvTransmitBCN(iobase) \ @@ -663,13 +662,13 @@ do { \ *(pdwValue) = ioread32(iobase + MAC_REG_ISR) #define MACvWriteISR(iobase, dwValue) \ - VNSvOutPortD(iobase + MAC_REG_ISR, dwValue) + iowrite32((u32)(dwValue), iobase + MAC_REG_ISR) #define MACvIntEnable(iobase, dwMask) \ - VNSvOutPortD(iobase + MAC_REG_IMR, dwMask) + iowrite32((u32)(dwMask), iobase + MAC_REG_IMR) #define MACvIntDisable(iobase) \ - VNSvOutPortD(iobase + MAC_REG_IMR, 0) + iowrite32(0, iobase + MAC_REG_IMR) #define MACvSelectPage0(iobase) \ iowrite8(0, iobase + MAC_REG_PAGE1SEL) @@ -685,7 +684,7 @@ do { \ unsigned long dwOrgValue; \ dwOrgValue = ioread32(iobase + MAC_REG_ENCFG); \ dwOrgValue = dwOrgValue | ENCFG_PROTECTMD; \ - VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \ + iowrite32((u32)(dwOrgValue), iobase + MAC_REG_ENCFG); \ } while (0) #define MACvDisableProtectMD(iobase) \ @@ -693,7 +692,7 @@ do { \ unsigned long dwOrgValue; \ dwOrgValue = ioread32(iobase + MAC_REG_ENCFG); \ dwOrgValue = dwOrgValue & ~ENCFG_PROTECTMD; \ - VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \ + iowrite32((u32)(dwOrgValue), iobase + MAC_REG_ENCFG); \ } while (0) #define MACvEnableBarkerPreambleMd(iobase) \ @@ -701,7 +700,7 @@ do { \ unsigned long dwOrgValue; \ dwOrgValue = ioread32(iobase + MAC_REG_ENCFG); \ dwOrgValue = dwOrgValue | ENCFG_BARKERPREAM; \ - VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \ + iowrite32((u32)(dwOrgValue), iobase + MAC_REG_ENCFG); \ } while (0) #define MACvDisableBarkerPreambleMd(iobase) \ @@ -709,7 +708,7 @@ do { \ unsigned long dwOrgValue; \ dwOrgValue = ioread32(iobase + MAC_REG_ENCFG); \ dwOrgValue = dwOrgValue & ~ENCFG_BARKERPREAM; \ - VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \ + iowrite32((u32)(dwOrgValue), iobase + MAC_REG_ENCFG); \ } while (0) #define MACvSetBBType(iobase, byTyp) \ @@ -718,7 +717,7 @@ do { \ dwOrgValue = ioread32(iobase + MAC_REG_ENCFG); \ dwOrgValue = dwOrgValue & ~ENCFG_BBTYPE_MASK; \ dwOrgValue = dwOrgValue | (unsigned long)byTyp; \ - VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \ + iowrite32((u32)(dwOrgValue), iobase + MAC_REG_ENCFG); \ } while (0) #define MACvGPIOIn(iobase, pbyValue) \ diff --git a/drivers/staging/vt6655/rf.c b/drivers/staging/vt6655/rf.c index 76c651d4da31..fbbf2ce80120 100644 --- a/drivers/staging/vt6655/rf.c +++ b/drivers/staging/vt6655/rf.c @@ -171,7 +171,7 @@ bool IFRFbWriteEmbedded(struct vnt_private *priv, unsigned long dwData) unsigned short ww; unsigned long dwValue; - VNSvOutPortD(iobase + MAC_REG_IFREGCTL, dwData); + iowrite32(dwData, iobase + MAC_REG_IFREGCTL); /* W_MAX_TIMEOUT is the timeout period */ for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { diff --git a/drivers/staging/vt6655/upc.h b/drivers/staging/vt6655/upc.h index c14b4d98c466..904a299cccb5 100644 --- a/drivers/staging/vt6655/upc.h +++ b/drivers/staging/vt6655/upc.h @@ -20,9 +20,6 @@ /* For memory mapped IO */ -#define VNSvOutPortD(dwIOAddress, dwData) \ - iowrite32((u32)(dwData), dwIOAddress) - #define PCAvDelayByIO(uDelayUnit) \ do { \ unsigned char __maybe_unused byData; \ -- 2.25.1