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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-90a8179e4fasm9733956d6.2.2026.08.13.00.45.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 Aug 2026 00:45:20 -0700 (PDT) Message-ID: Date: Thu, 13 Aug 2026 15:45:13 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] drm/msm/mdss: Enable INT2_GDSC alongside CORE_GDSC To: Dmitry Baryshkov Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Abel Vesa , Yuanjie Yang , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260720-msm_gdsc2-v1-0-4687866d6cb0@oss.qualcomm.com> <20260720-msm_gdsc2-v1-2-4687866d6cb0@oss.qualcomm.com> Content-Language: en-US From: Yongxing Mou In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=R5oz39RX c=1 sm=1 tr=0 ts=6a7d7616 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=YZRirGJidSSDptMLQzoA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEzMDA1MiBTYWx0ZWRfX7vqVJScKER/p vyoeL6TUYj3VE2c1tQmD6070M8scr3tXooHIIJZIFUj4jSnQO1aaGsVeP33xtY5zQt+EukJFTlh u0/6NR8LWnOt4ToI2kk2jsI6ltu5zU+uhUdZ3IZ+7e1sp5M9/jW8SPRS5+UQ17/pQcj9MbaN2eY dqJ1f9KRsnGkge8Cdhv+keHDI+U09E2JTPVPEigB26WATXruMJha5+ZstD41C2WeKzeqvuiTUpV vxYtCrs0KTo6BABEOyq3hzXH9YgKPLuYo2RMnXDPpXxk/rQCDiCtx9j9yVGCduNYapZkQWvJ563 iYBe/ANtRPaLhLtmz/3GsEiC4cCJ0d13QeOFKQF3o0MlspqNXwPLpeegflcE+TRN/N6r4wp6BSQ 1QsekRxSMwDByIe/PSBDTT+HJjHP2lGwgj/SKZyeSJunK1BbzuykWtQ3Kc8Ofi5BY2PZI9AgW0z PLjqOjhc4jmdDqNl8ig== X-Proofpoint-GUID: baY4pr8IMOge456p_1EdEgfIi_PUtMHh X-Proofpoint-Spam-Info: AW1haW4tMjYwODEzMDA1MiBTYWx0ZWRfX79GOyHWs/Vcx Dw8UQjOeWDMmZGKwG8sQ9Yxt8CUg51VoqUM7kScgdpnmIwrDjRzMrHFeQrq5jjHtghrpeclD8nE K/jkvuds/lcH3nxVlq18jCUzdAP0eKA= X-Proofpoint-ORIG-GUID: baY4pr8IMOge456p_1EdEgfIi_PUtMHh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-13_02,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 adultscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 phishscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608130052 On 7/22/2026 2:40 AM, Dmitry Baryshkov wrote: > On Mon, Jul 20, 2026 at 04:43:54PM +0800, Yongxing Mou wrote: >> Kaanapali (SM8750) and Glymur use two display power domains. >> CORE_GDSC powers the main display hardware while INT2_GDSC powers >> a subset of SSPP blocks (VIG2/VIG3/DMA5/DMA6). >> >> The MDSS driver currently relies on the default runtime PM handling >> and does not enable the secondary INT2_GDSC. As a result, display >> pipes backed by INT2_GDSC remain inaccessible. >> >> Attach and manage both power domains explicitly and enable them >> during MDSS runtime PM activation. >> >> Signed-off-by: Yongxing Mou >> --- >> drivers/gpu/drm/msm/msm_mdss.c | 53 +++++++++++++++++++++++++++++++++++++++++- >> 1 file changed, 52 insertions(+), 1 deletion(-) > > Why is it being handled in the MDSS rather than DPU? > Will move it next patchset. >> @@ -421,6 +451,27 @@ static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5 >> irq_set_chained_handler_and_data(irq, msm_mdss_irq, >> msm_mdss); >> >> + /* >> + * When two power domains are listed in DT, the core framework does not >> + * auto-attach either of them. Attach and manage both explicitly so >> + * that INT2_GDSC (needed for VIG2/VIG3) is enabled alongside the main >> + * CORE_GDSC. Single-domain platforms are unaffected. >> + */ >> + if (of_count_phandle_with_args(pdev->dev.of_node, "power-domains", >> + "#power-domain-cells") > 1) { >> + static const char * const mdss_pd_names[] = { "core", "int2" }; >> + static const struct dev_pm_domain_attach_data pd_data = { >> + .pd_names = mdss_pd_names, >> + .num_pd_names = ARRAY_SIZE(mdss_pd_names), >> + .pd_flags = PD_FLAG_NO_DEV_LINK, > > Can't you use DL_FLAG_PM_RUNTIME here? > Got it.Will ust it next patch. >> + }; >> + >> + ret = devm_pm_domain_attach_list(&pdev->dev, &pd_data, >> + &msm_mdss->pd_list); >> + if (ret < 0) >> + return ERR_PTR(ret); >> + } >> + >> pm_runtime_enable(&pdev->dev); >> >> return msm_mdss; >> >> -- >> 2.43.0 >> >