Re: [PATCH v4 01/13] dt-bindings: clock: renesas,r8a78000-cpg: Add CPG_SGDn_VIO_DP_{TX,OTHER}

[Krzysztof Kozlowski <krzk@kernel.org>]

On 09/11/2026 14:34, Paul Elder wrote:
> Add the CPG_SGDn_VIO_DP_TX and CPG_SGDn_VIO_DP_OTHER clocks that are
> used by FCPV, VSP, VCON, and DPTX cores.
> 
> It should be noted that there is likely a discrepancy regarding the
> clocks. In practice it ought not to be an issue as all the clocks derive
> from the same SGD1_VIO_MAIN clock and none of them are programmable or
> gateable.
> 
> According to the datasheet, the FCPV[BID] and VSPD cores use
> SGD*_VIO_DP_TXφ while the VSP[BI] cores use SGD*_VIO_DP_OTHERφ.
> However, educated guessing suggests that IP cores in the same pipeline
> should be using the same clocks:
> - FCPV[BI] -> VSP[BI]:                  SGD*_VIO_DP_OTHERφ
> - FCPVD -> VSPD -> VCON -> DPTX:        SGD*_VIO_DP_TXφ
> 
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> 


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof